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This work proposes an static random access memory (SRAM) with column-based split cell-VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28-nm FDSOI technology. The proposed CS-CVSS and DAWA techniques improve both half-selected (HS) static noise margin (SNM) and write margin. They also improve HS dynamic noise margin (HS-DNM) by leveraging write through virtual ground with reduced load in the proposed write port. The proposed 3T read port enhances sensing margin by minimizing read bitline leakage through negative gate-to-source voltage regardless of cell data. A 16-kb 9T SRAM test chip demonstrated the minimum operating voltage for write and read operations as 0.47 and 0.25 V, respectively. The minimum energy of 6.72 pJ is achieved at 0.5 V. [ABSTRACT FROM AUTHOR]

We propose a power-aware toggling-frequency actuator for an 1K-byte data-toggling SRAM. The actuator periodically toggles the stored data to balance the voltage stress in the SRAM cells to secure against data imprinting attacks. Our proposed actuator has three key features. First, our proposed actuator embodies a small duty cycle clock divider to divide the main clock and generate two toggling clocks. The small duty cycle clock minimizes toggling transistor turn-on time and reduces the leakage power in stand-by operation. Second, it leverages on the main clock of the data-toggling SRAM to generate the toggling clock without an additional clock generator. Third, our proposed actuator can scale the data toggling operation between high frequency for highly secure applications, and low frequency for low power applications. We implemented the 1K-byte data-toggling SRAM with the proposed toggling-frequency actuator based on 65nm CMOS technology. At higher toggling frequency (~ 1MHz), the data-toggling SRAM features less than 5% imprinting effect. At lower toggling frequency (~ 10kHz), the SRAM dissipates < 0.1mW toggling power where the secure data protection is less critical. When compared against the reported counterpart with toggling clock of 50% duty cycle, our proposed data-toggling SRAM (with ~ 3% duty cycle clock divider) occupies ~ 31% smaller IC area and dissipates ~ 29% lower toggling power, resulting in an overall reduction of ~ 51% area × power product. [ABSTRACT FROM AUTHOR]

This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of “0s”. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for “0”. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 μW and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V. [ABSTRACT FROM AUTHOR]

In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This paper presents a radiation resilient SRAM with a self-refresh scheme for lowering the number of errors in each row below a threshold number. The proposed self-refresh operation reads out the stored data and performs single error correction using a simple algorithm during its hold/idle mode. A 4KB SRAM test chip in 65nm CMOS technology demonstrates a significant reduction in errors with the self-refresh operation. When the SRAM test chip was exposed to accelerated proton radiation with an energy level of 39.38 MeV, the self-refresh scheme reduces the number of uncorrectable errors by $25\times $ and $8\times $ lesser for the fluence of $9.82\times 10^{11}$ particles/cm2 and $49.1\times 10^{11}$ particles/cm2, respectively. [ABSTRACT FROM AUTHOR]

This article presents an 8T static random access memory (SRAM) macro with vertical read wordline (RWL) and selective dual split power (SDSP) lines techniques. The proposed vertical RWL reduces dynamic energy consumption during read operation by charging and discharging only selected read bitlines (RBLs). The data-aware SDSP technique combined with vertical write bitlines enhances both the write margin (WM) and the static noise margin (SNM). A 16-kb SRAM test chip fabricated in 65-nm CMOS technology demonstrates the minimum energy consumption of 0.506 pJ at 0.4 V and the minimum operating voltage of 0.26 V. [ABSTRACT FROM AUTHOR]

Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized bitline scheme to eliminate the leakage dependence on data pattern and thus improves RBL sensing and its resilience against process, voltage, and temperature variations. In addition, we propose a fast local write-back (WB) technique to implement a half-select-free write operation. With hierarchical bitline architecture, it facilitates a local read and a subsequent fast WB action to secure the original data without performance degradation. A 16-kb SRAM test chip has been fabricated in a 65-nm CMOS technology and achieved the minimum operating voltage of 0.24 V with a read access time of 4.88 \mu \texts . [ABSTRACT FROM AUTHOR]

In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by using a column-based randomization engine (CBRE). This CBRE circuit randomizes data stored to SRAM. This makes distribution of “1” and “0” in each column close to 50%, significantly increasing bitline swing. To further improve the bitline swing, we employ bitline boost biasing and dynamic bitline keeper schemes. Based on the mentioned techniques, we fabricated a 256 rows × 128 columns (32 Kb) 8T SRAM array in 65 nm CMOS technology. In our silicon measurement, the SRAM array shows successful 200 mV operation at room temperature, where energy consumption and access time are 1 pJ and 2.5 s, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents an 8-Kbit low-power SRAM for high-temperature (up to 300 °C) applications. For reliable low-voltage operation, we employed a decoupled 8T SRAM cell structure. To minimize the performance variations caused by the wide operating temperate range, supply voltage was selected in the near-threshold region. A temperature-aware bitline sensing margin enhancement technique is proposed to mitigate the impact of significantly increased bitline leakage on bitline swing and sensing window. A temperature-tracking control circuit generates bias voltage for optimal pull-up current for realizing the proposed enhancement technique. Test chips were fabricated in a commercial 5 V, 1.0 µm SOI technology. Test chip measurement demonstrates successful operation down to 2 V at 300 °C. The average energy of 0.94 pJ was achieved at 2 V and 300 °C. [ABSTRACT FROM AUTHOR]

This brief presents a negative bias temperature instability (BTI)/positive BTI-aware write-wordline (WWL) voltage control technique for improving degraded cell stability of half-selected cells without extra power consumption. After BTI aging, the proposed lowering WWL voltage recovers the degraded cell stability without scarifying the write margin. Finally, we also present a sample circuit implementation of the proposed WWL voltage control scheme. [ABSTRACT FROM PUBLISHER]