11 results on '"Kim, Tony"'
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2. A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection.
- Author
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Ho, Weng-Geng, Chong, Kwen-Siong, Kim, Tony Tae-Hyoung, and Gwee, Bah-Hwee
- Abstract
We propose a power-aware toggling-frequency actuator for an 1K-byte data-toggling SRAM. The actuator periodically toggles the stored data to balance the voltage stress in the SRAM cells to secure against data imprinting attacks. Our proposed actuator has three key features. First, our proposed actuator embodies a small duty cycle clock divider to divide the main clock and generate two toggling clocks. The small duty cycle clock minimizes toggling transistor turn-on time and reduces the leakage power in stand-by operation. Second, it leverages on the main clock of the data-toggling SRAM to generate the toggling clock without an additional clock generator. Third, our proposed actuator can scale the data toggling operation between high frequency for highly secure applications, and low frequency for low power applications. We implemented the 1K-byte data-toggling SRAM with the proposed toggling-frequency actuator based on 65nm CMOS technology. At higher toggling frequency (~ 1MHz), the data-toggling SRAM features less than 5% imprinting effect. At lower toggling frequency (~ 10kHz), the SRAM dissipates < 0.1mW toggling power where the secure data protection is less critical. When compared against the reported counterpart with toggling clock of 50% duty cycle, our proposed data-toggling SRAM (with ~ 3% duty cycle clock divider) occupies ~ 31% smaller IC area and dissipates ~ 29% lower toggling power, resulting in an overall reduction of ~ 51% area × power product. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
3. Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding.
- Author
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Do, Anh Tuan, Zeinolabedin, Seyed Mohammad Ali, and Kim, Tony Tae-Hyoung
- Abstract
This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of “0s”. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for “0”. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 μW and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
4. SRAM Radiation Hardening Through Self-Refresh Operation and Error Correction.
- Author
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Siddiqui, M. Sultan M., Ruchi, Sharma, Van Le, Loi, Yoo, Taegeun, Chang, Ik-Joon, and Kim, Tony Tae-Hyoung
- Abstract
In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This paper presents a radiation resilient SRAM with a self-refresh scheme for lowering the number of errors in each row below a threshold number. The proposed self-refresh operation reads out the stored data and performs single error correction using a simple algorithm during its hold/idle mode. A 4KB SRAM test chip in 65nm CMOS technology demonstrates a significant reduction in errors with the self-refresh operation. When the SRAM test chip was exposed to accelerated proton radiation with an energy level of 39.38 MeV, the self-refresh scheme reduces the number of uncorrectable errors by $25\times $ and $8\times $ lesser for the fluence of $9.82\times 10^{11}$ particles/cm2 and $49.1\times 10^{11}$ particles/cm2, respectively. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
5. A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines.
- Author
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Lu, Lu, Yoo, Taegeun, Le, Van Loi, and Kim, Tony Tae-Hyoung
- Subjects
ELECTRIC lines ,STATIC random access memory ,STATIC random access memory chips ,ENERGY consumption - Abstract
This article presents an 8T static random access memory (SRAM) macro with vertical read wordline (RWL) and selective dual split power (SDSP) lines techniques. The proposed vertical RWL reduces dynamic energy consumption during read operation by charging and discharging only selected read bitlines (RBLs). The data-aware SDSP technique combined with vertical write bitlines enhances both the write margin (WM) and the static noise margin (SNM). A 16-kb SRAM test chip fabricated in 65-nm CMOS technology demonstrates the minimum energy consumption of 0.506 pJ at 0.4 V and the minimum operating voltage of 0.26 V. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
6. A Secure Data-Toggling SRAM for Confidential Data Protection.
- Author
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Ho, Weng-Geng, Chong, Kwen-Siong, Kim, Tony Tae-Hyoung, and Gwee, Bah-Hwee
- Subjects
DATA protection ,STATIC random access memory - Abstract
We study the security feature of static random access memory (SRAM) against the data imprinting attack and provide a solution to protect the SRAM from this attack. There are four main contributions in this paper. First, the negative-bias temperature-instability (NBTI) degradation of PMOS transistors in the conventional SRAM cell that causes the data imprinting effect is explained. Second, the data imprinting effect that leaks the stored information in the conventional SRAM cell is investigated. Third, a novel low transistor-count transmission-gate-based master–slave SRAM cell is proposed to periodically toggle the stored data for reducing the data imprinting effect. Fourth, an efficient imprinting analysis flow is proposed to evaluate the proposed data-toggling SRAM for quantifying the data imprinting effect. Based on a 65-nm CMOS process, we implement and prototype the proposed 1k-byte data-toggling SRAM design. We perform our imprinting analysis flow on various SRAM ICs and benchmark our proposed data-toggling SRAM IC against the non-toggling SRAM IC and a commercial Lyontek SRAM IC. From the measurement results, the non-toggling SRAM and Lyontek SRAM suffer from 60% and 81% data imprinting effects, respectively, whereas our data-toggling SRAM has only 11% data imprinting effect (at 160-kHz toggling frequency). The data-toggling SRAM could switch between high security (< 5% data imprinting effect) high power mode for hardware security applications and low power (< 0.1mW) low security mode for power-saving applications. Particularly, our data-toggling SRAM could feature as low as ~1% data imprinting effect when increasing the toggling frequency to 1.6 MHz by compromising the power dissipation. Using the image analysis flow, the stored information is revealed in both the non-toggling and Lyontek SRAM ICs but is well protected in the proposed data-toggling SRAM IC. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
7. Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs.
- Author
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Wang, Bo, Li, Qi, and Kim, Tony Tae-Hyoung
- Subjects
ELECTRIC potential measurement ,TEMPERATURE measurements ,FABRICATION (Manufacturing) ,CELL analysis ,TECHNOLOGICAL innovations - Abstract
Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized bitline scheme to eliminate the leakage dependence on data pattern and thus improves RBL sensing and its resilience against process, voltage, and temperature variations. In addition, we propose a fast local write-back (WB) technique to implement a half-select-free write operation. With hierarchical bitline architecture, it facilitates a local read and a subsequent fast WB action to secure the original data without performance degradation. A 16-kb SRAM test chip has been fabricated in a 65-nm CMOS technology and achieved the minimum operating voltage of 0.24 V with a read access time of 4.88 \mu \texts . [ABSTRACT FROM AUTHOR]
- Published
- 2016
- Full Text
- View/download PDF
8. 0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization.
- Author
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Do, Anh Tuan, Lee, Zhao Chuan, Wang, Bo, Chang, Ik-Joon, Liu, Xin, and Kim, Tony Tae-Hyoung
- Subjects
REMOTE sensing ,RANDOMIZATION (Statistics) ,STATIC random access memory chips ,SILICON testing ,ENERGY consumption ,COMPUTER software - Abstract
In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by using a column-based randomization engine (CBRE). This CBRE circuit randomizes data stored to SRAM. This makes distribution of “1” and “0” in each column close to 50%, significantly increasing bitline swing. To further improve the bitline swing, we employ bitline boost biasing and dynamic bitline keeper schemes. Based on the mentioned techniques, we fabricated a 256 rows × 128 columns (32 Kb) 8T SRAM array in 65 nm CMOS technology. In our silicon measurement, the SRAM array shows successful 200 mV operation at room temperature, where energy consumption and access time are 1 pJ and 2.5 s, respectively. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
- Full Text
- View/download PDF
9. Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C.
- Author
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Kim, Tony Tae-Hyoung and Le Ba, Ngoc
- Subjects
LOW voltage integrated circuits ,HIGH temperature electronics ,DIGITAL electronics ,COMPLEMENTARY metal oxide semiconductors ,NANOELECTROMECHANICAL systems - Abstract
This paper presents an 8-Kbit low-power SRAM for high-temperature (up to 300 °C) applications. For reliable low-voltage operation, we employed a decoupled 8T SRAM cell structure. To minimize the performance variations caused by the wide operating temperate range, supply voltage was selected in the near-threshold region. A temperature-aware bitline sensing margin enhancement technique is proposed to mitigate the impact of significantly increased bitline leakage on bitline swing and sensing window. A temperature-tracking control circuit generates bias voltage for optimal pull-up current for realizing the proposed enhancement technique. Test chips were fabricated in a commercial 5 V, 1.0 µm SOI technology. Test chip measurement demonstrates successful operation down to 2 V at 300 °C. The average energy of 0.94 pJ was achieved at 2 V and 300 °C. [ABSTRACT FROM AUTHOR]
- Published
- 2014
- Full Text
- View/download PDF
10. Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement.
- Author
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Wang, Bo, Nguyen, Truc Quynh, Do, Anh Tuan, Zhou, Jun, Je, Minkyu, and Kim, Tony Tae-Hyoung
- Subjects
LOW voltage systems ,STATIC random access memory chips ,CAD/CAM systems ,STRAY currents ,ASSOCIATIVE storage ,ELECTRIC power consumption management - Abstract
This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 \mu s. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V\sim0.6 V by the proposed CAM-assisted circuit. [ABSTRACT FROM AUTHOR]
- Published
- 2015
- Full Text
- View/download PDF
11. NBTI/PBTI-Aware WWL Voltage Control for Half-Selected Cell Stability Improvement.
- Author
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Lee, Zhao Chuan, Leong, Kam Chew, Kong, Zhi Hui, and Kim, Tony Tae-Hyoung
- Abstract
This brief presents a negative bias temperature instability (BTI)/positive BTI-aware write-wordline (WWL) voltage control technique for improving degraded cell stability of half-selected cells without extra power consumption. After BTI aging, the proposed lowering WWL voltage recovers the degraded cell stability without scarifying the write margin. Finally, we also present a sample circuit implementation of the proposed WWL voltage control scheme. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
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