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With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices degrade circuit performance and even lead to functional failure. The stress analysis is critical to evaluate the influence of aging effects on digital circuits. Some related analytical work has recently focused on reliability-aware circuit analysis. Nevertheless, the aging dependence among different devices is not considered, which will induce errors of degradation evaluation in the digital circuit. In order to improve the accuracy of reliability-aware static timing analysis, an improved analytical method is proposed by employing logical resolving. Experimental results show that the proposed method has a better evaluation accuracy of aging path delay than traditional strategies. For aging timing evaluation on aging paths, excessive pessimism can be reduced by employing the proposed method. And, a 378× speedup is achieved while having a 0.56% relative error compared with precise SPICE simulation. Moreover, the circuit performance sacrifice of an aging-aware synthesis flow with the proposed method can be decreased. Due to the high efficiency and high accuracy, the proposed method can meet the speed demands of large-scale digital circuit reliability analysis while achieving transistor simulation accuracy. [ABSTRACT FROM AUTHOR]

With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices degrade circuit performance and even lead to functional failure. The stress analysis is critical to evaluate the influence of aging effects on digital circuits. Some related analytical work has recently focused on reliability-aware circuit analysis. Nevertheless, the aging dependence among different devices is not considered, which will induce errors of degradation evaluation in the digital circuit. In order to improve the accuracy of reliability-aware static timing analysis, an improved analytical method is proposed by employing logical resolving. Experimental results show that the proposed method has a better evaluation accuracy of aging path delay than traditional strategies. For aging timing evaluation on aging paths, excessive pessimism can be reduced by employing the proposed method. And, a 378× speedup is achieved while having a 0.56% relative error compared with precise SPICE simulation. Moreover, the circuit performance sacrifice of an aging-aware synthesis flow with the proposed method can be decreased. Due to the high efficiency and high accuracy, the proposed method can meet the speed demands of large-scale digital circuit reliability analysis while achieving transistor simulation accuracy.