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Deep convolutional neural networks (DCNNs) have achieved state-of-the-art performance in classification, natural language processing (NLP), and regression tasks. However, there is still a great gap between DCNNs and the human brain in terms of computation efficiency. Inspired by neural synaptic plasticity and stochastic computing (SC), we propose neural synaptic plasticity-inspired computing (NSPC) to simulate the human brain’s neural network activity for inference tasks with simple logic gates. The multiplication and accumulation (MAC) is transformed by the wire connectivity in NSPC, which only requires bundles of wires and small width adders. To this end, the NSPC imitates the structure of neural synaptic plasticity from a circuit wires connection perspective. Furthermore, from the principle of NSPC, we use a data mapping method to convert the convolution operations to matrix multiplications. Based on the methodology of NSPC, fully-pipelined and low latency architecture is designed. The proposed NSPC accelerator exhibits high hardware efficiency while maintaining a comparable network accuracy level. The NSPC based DCNN accelerator (NSPC-CNN) processes DCNN at $1.5625M$ images/ $s$ with a power dissipation of $15.42~W$ and an area of $36.4~mm^{2}$. The NSPC based deep neural network (DNN) accelerator (NSPC-DNN) that implements three fully connected layers DNN consumes only $6.6~mm^{2}$ area and $2.93~W$ power, and achieves a throughput of $400M$ images/ $s$. Compared with conventional fixed-point implementations, the NSPC-CNN achieves $2.77 \times $ area efficiency, $2.25 \times $ power efficiency; the proposed NSPC-DNN exhibits $2.31 \times $ area efficiency and $2.09 \times $ power efficiency. [ABSTRACT FROM AUTHOR]

Sparse code multiple access (SCMA) is a promising multiple access technology candidate for the next-generation communication system, which can dramatically improve spectral efficiency. However, the major challenge of SCMA is the very high detection complexity. Stochastic computing is a new number representation, which can carry out complex computations with very simple logics. In this paper, we extend the application of stochastic computing to SCMA detection and propose a low complexity stochastic SCMA detector. We also design three novel stochastic logic architectures: a new low hardware cost bit stream generation architecture, a low hardware cost stochastic function node update architecture and a fast converging stochastic variable node update architecture. Analysis and simulation results show that the proposed stochastic SCMA detector saves 69% complexity compared with the traditional SCMA detectors with a comparable bit error rate performance. The synthesis results with SIMC 65-nm CMOS technology show that the proposed stochastic SCMA detector achieves 640 Mbps total system throughput with only 1.45-mm $^{{{2}}}$ cell area. [ABSTRACT FROM PUBLISHER]