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A physics-based SPICE model that takes into account the statistical impacts of both successive and progressive oxide breakdowns is presented to evaluate the time-dependent dielectric breakdown (TDDB)-induced performance degradation in static random access memory cells and peripheral circuits. The postbreakdown $I$ – V$ characteristics and the distribution of time to breakdown (t_{\rm {BD}}) have been verified against experimental data from 45-nm Silicon on insulator technology. We show that peripheral circuits, such as word-line driver, sense amplifier, and write driver, also contribute to degradation of performance during read and write operations. Using the model, the statistical impact of TDDB on sensing delay and write access time can be properly modeled for read and write failure prediction. [ABSTRACT FROM AUTHOR]

This paper analyzes the root cause of performance degradation and the impact of hot-carrier injection (HCI) on the lifetime prediction of an $LC$ voltage-controlled oscillator ( $LC$ -VCO). Observed from both constant voltage stress and ramped voltage stress tests, it is shown that the dominant degradation mechanism shifts from a negative bias temperature instability to an HCI due to the accelerated aging condition. Furthermore, simulations show that a frequency increase of degraded VCO is mainly attributed to the degradation in the pMOSFET of a cross-couple pair, while the degradations in the pMOSFET and nMOSFET have relatively the same impact on the startup voltage shift. Compared with the frequency change, the degradation of the startup voltage of an $LC$ -VCO is less sensitive to device width. Based on the observed results, methodologies to optimize the reliability tests and mitigate the frequency shift of $LC$ -VCO are proposed. [ABSTRACT FROM PUBLISHER]

Positive bias temperature instability (PBTI) has become one of the major reliability concerns in the present day CMOS technology. The PBTI mostly degrades the performance of high- \(\kappa \) /metal gate (HK/MG) nMOSFETs and is dominated by time dependent stress induced trap generation. The PBTI models proposed so far in different literature are deterministic in nature and overlook the randomness of the temporal degradation of transistor threshold voltage, \(V_{\rm th}\) . In this paper, we present a stochastic model for PBTI to predict the behavior of HK/MG nMOSFETs under inversion mode stress. The model is scalable and is verified against experimental data from two different groups. Our model separately considers each trap to predict their impact on device performance. The simulations are carried out at accelerated voltage and temperature conditions and we noted the variations in \(V_{\rm th}\) . In addition, we have analyzed the impact of PBTI on the performance of a ring oscillator and concluded that the circuit speed suffers significant degradation due to this effect. We have also observed that the adverse effect of PBTI becomes more severe as we go deeper into the nanometer technology. [ABSTRACT FROM AUTHOR]

The electrical performance of low-temperature polysilicon (LTPS) thin-film transistors (TFTs) has improved considerably in the last decade, due to the flourishing active-matrix liquid crystal display industry. However, there is a need to further scale down LTPS TFT devices on flexible substrates to explore other application domains. In order to realize this goal, self-heating-induced negative bias temperature instability (NBTI) in LTPS TFTs needs to be modeled to determine its effect on transistor degradation and to develop mitigation techniques. Although the characteristics of NBTI for TFTs are widely known, the effects of device geometry and substrate on temperature-dependent NBTI have not been considered. In this paper, for the first time, a self-consistent electrothermal model that considers the effects of device geometry, substrate, and stress conditions on NBTI is proposed. With the proposed modeling methodology, we show the significant impact of device geometry, substrate, and supply voltage on NBTI in LTPS TFTs. [ABSTRACT FROM AUTHOR]

In this letter, we present a physics-based compact SPICE model to predict statistical time-dependent dielectric breakdown (TDDB) in nanoscale circuits. In our model, an increase in the gate leakage current ( IG\BD) induced by TDDB is estimated using a quantum point contact (QPC) model depending on temperature. In addition, IG\BD is based on the statistics of time to breakdown (BD) ($t_{{\rm BD}}$ ) and location of percolation path ($x_{{\rm BD}}$ ) in the channel considering third successive BDs. We show that the model can be easily implemented to circuit simulators to predict the degradation of circuit lifetime. With the proposed model, we validated post-BD I–V characteristics with experimental data in ultrathin oxide technology. [ABSTRACT FROM PUBLISHER]