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In this work, the polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with double gates and nanosheet (NSH) channel structures were fabricated to investigate the impact of NSH channel thickness (tSi) ranging from 15 nm to 2 nm on device performance and reliability. Thinning tSi from 15 nm to 10 nm resulted in improved control of channel potential by the gate voltage, leading to a decreased threshold voltage (VTH) and subthreshold swing (SS). However, further reduction of tSi to 5 nm, while continuing to decrease SS, caused an increase in VTH due to the grain size reduction and quantum confinement (QC) effects. Lastly, reducing tSi to 2 nm resulted in an increase in both SS and VTH mainly due to the QC effect. In terms of reliability, under a fixed positive gate bias stress condition, thinning tSi enhanced the electric field stress, leading to more severe device damage. However, due to the enhanced ability of gate voltage control over the channel potential and the buried channel effect on electron transport resulting from thinning the channel thickness, there exists an optimal range between 10 nm and 5 nm for the selection of tSi in terms of the degradation of VTH, SS, and on-state current. Consequently, it is evident that for transistors utilizing NSH channels, the selection of tSi is not a case of “the thinner, the better.” This finding highlights the need to consider the optimal tSi range between 10 nm and 5 nm, balancing the performance and reliability aspects of the device design. [ABSTRACT FROM AUTHOR]

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance (${G}_{m\_{}{\text {max}}}$) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage (${V}_{\text {BG}}$) operation mode, the ${V}_{\text {BG}}$ can provide a wide threshold voltage (${V}_{\text {TH}}$) tuning range ~2 V when the ${V}_{\text {BG}}$ is modulated from 0 to −4 V. The negative ${V}_{\text {BG}}$ bias stress would induce electron injection from the BG, resulting in positive ${V}_{\text {TH}}$ shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative ${V}_{\text {BG}}$ stress, using ${V}_{\text {BG}}$ to modulate the ${V}_{\text {TH}}$ of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent ${V}_{\text {BG}}$ to adjust the ${V}_{\text {TH}}$ of the JL-TFTs to meet the multiple- ${V}_{\text {TH}}$ requirement of advanced integrated circuits. [ABSTRACT FROM AUTHOR]

In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage ($V_{\text {TH}}$) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to −0.82 V, respectively. The degradation of on-state current is also improved significantly from −87% to −40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step $V_{\text {TH}}$ shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C. [ABSTRACT FROM AUTHOR]

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT. [ABSTRACT FROM AUTHOR]

Hot-carrier stress (HCS) characteristics of polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors are investigated and compared with the conventional poly-Si thin-film transistors (TFTs). After HCS with VDS = 2VGS = 20 V for 1000 s, poly-Si TFT exhibits significant ON-state current (Ion) degradation ~85% and two-step subthreshold swing (SS) behavior due to the serious lattice damage between the pinch-off point and the drain. For the poly-Si tunnel field-effect transistor (TFET), less Ion degradation ~70% is observed. In addition, the stress drain voltage (VDS) effect of the HCS is also studied. When the stress VDS is increased from 10 to 15 V, the poly-Si TFETs exhibit more obvious stressed Ion degradation (~24.4%) than that of poly-Si TFTs (~6.5%). When the stress VDS is further increased from 15 to 20 V, the poly-Si TFETs exhibit less stressed Ion degradation (~62.4%) than that of poly-Si TFTs (~85%). Because the increase in the stress drain voltage is dropped in the pinch-off region of the poly-Si TFETs after the pinch-off phenomenon occurs, resulting in less impact on the stress field at the tunnel junction. When the channel length is decreased, the results show that the HCS effect of poly-Si TFETs is insensitive to the channel length, and the poly-Si TFTs show more serious electrical degradation and breakdown behavior with the scaling down of the channel length. The stronger HCS immunity of poly-Si TFETs would be an important advantage to replacing poly-Si TFTs for applications of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]