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In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ($\alpha $ -IGZO n-FET) on a SiO2/Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing (SS) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage (${V}_{\text {TH}}$), and SS of 91 cm2/ $\text{V}\cdot \text{s}$ , −0.26 V, 225 mV/decade, respectively, and those for the $\alpha $ -IGZO n-FET are 58 cm2/ $\text{V}\cdot \text{s}$ , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NMH of 0.33 V, NML of 0.22 V, and power consumption of less than 0.03 mW at ${V}_{\text {DD}}$ of 1 V. [ABSTRACT FROM AUTHOR]

Germanium–tin (GeSn) p-channel fin field-effect transistor (p-FinFET) was realized on a novel GeSn-on-insulator (GeSnOI) substrate. The high-quality GeSnOI substrate was formed using direct wafer bonding technique and was layer-transferred from a 300-mm GeSn/Ge/Si donor wafer. Material quality was examined using atomic force microscopy, high-resolution transmission electron microscopy, Raman spectroscopy, and high-resolution X-ray diffraction. The fabricated GeSn p-FinFETs exhibit a small subthreshold swing (${S}$) of 79 mV/decade at ${V}_{\text {DS}}$ of −0.05 V (by a device with ${L}_{\text {CH}}$ of 200 nm and ${W}_{\text {Fin}}$ of 30 nm), good control of short channel effects, and high intrinsic transconductance (${G}_{m,\text {int}} = 702\,\,\mu \text {S}/\mu \text{m}$ at ${V}_{\text {DS}}$ of −0.5 V for ${L}_{\text {CH}}$ of 80 nm). Low-temperature mobility analysis was performed on the GeSn p-FinFETs. High effective hole mobility ($\mu _{\text {eff}}$) (210 cm2/ $\text {V}\cdot \text {s}$ at 290 K and 398 cm2/ $\text {V}\cdot \text {s}$ at 5 K) is achieved. The GeSn p-FinFETs presented in this paper exhibit the highest ${G}_{m,\text {int}}/{S}_{\text {sat}}$ at ${V}_{\text {DS}}$ of −0.5 V for all the reported GeSn p-FETs to date. [ABSTRACT FROM AUTHOR]

We report on the growth of In0.30Ga0.70As channel high electron mobility transistor (HEMT) epi-layers on a 200-mm Si substrate by metal-organic-chemical-vapor-deposition. The HEMT layers were grown on the Si substrate by using a ~3- \mu \textm thick epitaxial buffer composing of a Ge layer, a GaAs layer, and a compositionally graded and strain relaxed InAlAs layer. The optimized epitaxy has a threading dislocation density of less than 2 \times 10^7 cm−2 and a root mean square surface roughness of ~6.7 nm. The device active layers include a \delta -doped InAlAs bottom barrier, a ~15-nm thick InGaAs channel, a ~8-nm InGaP top barrier layer and a heavily doped InGaAs contact layer. MOSHEMTs with channel length down to 130 nm were fabricated. The devices achieve a peak transconductance of \sim 450 ~\mu \textS/ \mu \textm at V D of 0.5 V. The peak effective mobility ( \mu \text {eff} ) in a device with a channel length of 20 \mu \textm device channel was ~3700 cm2/ \textV \cdot \texts . [ABSTRACT FROM AUTHOR]

Integration of InxGa1–xAs n-MOSFETs and SiyGe1–y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics. [ABSTRACT FROM PUBLISHER]