1. Back-End-of-Line Compatible Fully Depleted CMOS Inverters Employing Ge p-FETs and α-InGaZnO n-FETs.
- Author
-
Kang, Yuye, Han, Kaizhen, Kumar, Annie, Wang, Chengkuan, Sun, Chen, Zhou, Zuopu, Zhou, Jiuren, and Gong, Xiao
- Subjects
INDIUM gallium zinc oxide ,FIELD-effect transistors ,THRESHOLD voltage ,GERMANIUM ,INTEGRATED circuits ,HIGH temperatures - Abstract
In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ($\alpha $ -IGZO n-FET) on a SiO2/Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing (SS) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage (${V}_{\text {TH}}$), and SS of 91 cm2/ $\text{V}\cdot \text{s}$ , −0.26 V, 225 mV/decade, respectively, and those for the $\alpha $ -IGZO n-FET are 58 cm2/ $\text{V}\cdot \text{s}$ , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NMH of 0.33 V, NML of 0.22 V, and power consumption of less than 0.03 mW at ${V}_{\text {DD}}$ of 1 V. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF