Search

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field. [ABSTRACT FROM AUTHOR]

Purpose: This paper presents a novel low-power, low input offset rail-to-rail comparator that is suitable for a digital dominant successive approximation resistor analog-to-digital converter. The proposed comparator is based on traditional inverters cascaded to amplify analog signals and digital logic level conversion. The absence of a direct path between the high-swing output node and the input node restricts kickback noise. Design/methodology/approach: The proposed circuit is designed and simulated using UMC 28 nm and 40 nm CMOS technology. The simulated power consumption using UMC 40 nm CMOS technology is 6.2084 μW at 1.1 V (330.8nW at 700 mV) supply voltage at the 2.5 MHz clock frequency. Similarly, simulated power consumption using UMC 28 nm technology is 0.04104μW at 900 mV (0.0097μW at 600 mV) and supply voltage operating at 66.66 MHz clock frequency with a resolution of a maximum of 12 bits, therefore, a reduction of more than 90% in power consumption observed by scaling technology node. Findings: The conventional power-efficient clock-controlled latched comparator does not have a static current during the entire operation. The main drawbacks are the limited input range and the the kickback noise. However, a large voltage swing on the drain of a differential pair, due to this current feeding through a parasitic drain gate capacitor to the input node and the presence of source impedance, results in kickback noise. The performance of the ADC can be hampered by excessive kickback noise, which can eventually cause an incorrect comparator output. An inverter-based comparator is reported, where the input range is rail-to-rail and operates at moderate speed. Modern scaled technologies have better matching among transistors, i.e. matching of switching threshold voltage achieved by selecting suitable aspect ratios of transistors (cascaded inverters). Inverter-based dynamic comparators are inherently power-scalable and switching threshold voltage scales with supply voltage variation. Therefore, the amplification operation is not hampered by the reduction of the supply voltage. Originality/value: The proposed architecture is compared with a set of existing hardware architectures to analyse various design metrics, such as low input offset, power scalability to maintain the resolution of the comparator, and low kickback noise. [ABSTRACT FROM AUTHOR]

This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40nm CMOS technology process. The area of the proposed comparator is 28.025μm2. When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9V supply voltage, 25∘C, 1 GHz operational frequency, typical process corner (tt), and 1mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9ps from meta-stability analysis, energy per comparison of 0.175pJ/comparison and a kickback noise of 44.55 μA. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications. [ABSTRACT FROM AUTHOR]

This paper presents a background calibration method assisted with noise-shaping, for a 10-b bridged SAR ADC. It proposes calibrating the mismatches from the MSB capacitors using the LSBs. First-order noise-shaping has been employed to facilitate the calibration as well as the analog-to-digital conversion. Since noise-shaping is able to shape both the comparator input and quantization noise, it is expected to improve the calibration effects as well as the SNR, for the SAR ADC. Measurement results show, upon the proposed calibration, the SAR's INL and SNR are improved by 3 LSB and 9 dB, respectively, compared to when the noise shaping is off. Fabricated using a 55 nm CMOS MOMCAP technology and tested with a −2.5 dB sinewave input, the bridged SAR ADC achieves an SNR of 62.2 dB and an INL better than 1 LSB, when consuming a power of 7 2 μ W , at a supply voltage of 1.2 V and sampling frequency of 50 kHz. The ADC's active area is 3 0 0 × 3 8 0 μ m 2 . [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65 nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low power comparator with minimum delay and low offset, used in successive approximation register analog-to-digital converters (SAR ADCs) for biomedical system-on-chips (SoCs). To reduce the power consumption, the proposed comparator is designed with a minimum supply voltage in the sub-threshold region. Additionally, intermediate switches are utilized in the design to serve two purposes: 1) breaking the connection between the latch and preamplifier parts during the pre-charge phase to reduce power consumption, 2) reducing the parasitic resistance of the discharge path during the evaluation phase to enhance effective transconductance of the latch ( g m e f f , l a t c h ). Furthermore, the proposed design incorporates, two transistors as auxiliary paths to increase the speed of discharging in the latching process. Overall, the proposed design aims to achieve a low power and high-performance comparator simulated at a frequency of 50 kHz using TSMC 65nm CMOS technology. The post-layout simulation results show that the proposed structure enjoyed from an ultra-low power consumption of 141.4 pW as well as excellent delay and offset with 357 ns and 3.32 mV values, respectively. The occupied area of the designed layout for the proposed comparator is 106.8 μm2 allowed us to embed it in multi-channel recording system on chips (SoCs). The Figure of Merit (FoM) of the proposed comparator is 0.000463 fVW/Hz. Moreover, the proposed comparator has been validated by using it in successive approximation conversion algorithm with a sampling frequency of 1 kS/s. [ABSTRACT FROM AUTHOR]

This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is 235.23×301.67 μm2. [ABSTRACT FROM AUTHOR]

The increasing demand for low voltage, power efficient, high-speed analog-to-digital converters (ADCs) results in the improvement of speed and power of regenerative dynamic comparator. In this paper, a dual-tail dynamic comparator is used with two extra transistors in the latch stage. These extra transistors help in the increase of transconductance of the latch stage, which helps decrease the delay of the proposed comparator. Mathematical analysis is done for the proposed architecture; this gives the idea of reducing the delay of the comparator with an increase in the transconductance of the comparator. The simulation and layout of the proposed comparator are done on the Cadence software with 90 nm CMOS technology. This proposed design is simulated with a 2 GHz clock frequency at supply voltage of 1 V. The proposed architecture consumes a power of 39.19 μ W and a delay of 143.12 ps at 1 V supply voltage, 5 mV input difference voltage and 0.9 V common mode voltage. The Monte Carlo simulation of the proposed architecture for power, delay, power delay product (PDP) and offset is also demonstrated in this paper. Process corner analysis is done for power, delay and PDP. [ABSTRACT FROM AUTHOR]

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital). [ABSTRACT FROM AUTHOR]

This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low‐power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto‐zero period. With the combination of the proposed techniques, the power consumption of the single‐slope ADC can be effectively saved while suppressing the dynamic current. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

Forward body biasing (FBB) has often been exploited in the literature for improving the performance of both analog and digital building blocks. Recent works have explored the application of FBB variants to mixed-signal electronics and in particular to dynamic comparators, where these techniques can help to relax the trade-off between speed and power consumption at medium and low supply voltages. However, the literature lacks a structured analysis of the solutions that have been developed and of the trade-offs that affect them. This work attempts to fill the gap by providing a survey of the application of FBB techniques to dynamic comparators. The analysis focuses on the two most popular dynamic comparator topologies, the Strong Arm latch and Elzakker's comparator. Several FBB variants are examined from a theoretical point of view. Moreover, the benefits and the limitations of the different approaches are assessed in terms of the main figures of merit through a systematic campaign of simulations in a 55 nm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents the realization of binary and floating-point comparators on FPGA. The implementation is done by exploiting the primitive instantiation of FPGA resources which has enabled a significant improvement in resource utilization in terms of Look-Up Table (LUT) usage and overall combinational path delay when compared to the conventional inference approach. The comparator architectures are implemented using Vivado 2020.1 and ISE Design Suite 14.7 environment on multiple Xilinx FPGA platforms and are compared with the existing designs. The results indicate an improvement of 33.33% and 45.45% in LUT utilization, 14.41% and 30.73% in delay for 32-bit and 64-bit binary comparators respectively, compared to the existing architectures. The proposed floating-point comparator requires 88.57% and 285.29% lesser LUTs for single precision and double precision representation respectively, compared to the existing design. [ABSTRACT FROM AUTHOR]

The Emerging biomedical applications such as electrocardiography, electroencephalogram, wireless implantable devices have required optimized power-based SAR ADC in them to reduce package cost and to extend battery life. In view of power optimized SAR ADC, a dynamic controlled comparator with novel static power reduction logic incorporated with common mode kickback noise reduction technique is designed at 45 nm technology in CADENCE Virtuoso in this paper. Designed comparator is analyzed in terms of performance parameters; static power dissipation, transient power dissipation, maximum sampling rate, offset voltage and delay. Simulation and behaviour modeling analyses of proposed dynamic comparator has resulted in five times reduction in static power dissipation along with optimization of transient power and sampling rate as well compared to previously available double tail dynamic comparator. Moreover, it has been mentioned that proposed dynamic comparator is dissipating 2.36 pW of static power and 3.59 nW of transient power with sampling rate of 240 KS/s at 0.5 V. Further, the kickback noise of proposed design is limited to 4.7 mV with maximum delay of 124 ps. Finally, the novel outcomes of proposed comparator are the optimization in required parameters such as power, delay, offset voltage and kickback noise for biomedical applications as compared to double tail dynamic comparator. The proposed consideration for SAR ADC can become a backbone for low power biomedical applications. [ABSTRACT FROM AUTHOR]

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of high-performance N-bit digital comparators for use in modern digital systems. Digital comparators are fundamental building blocks in many electronic systems, performing the critical task of comparing two digital values and generating an output indicating their relative magnitudes. For implementing N-bit digital comparator a new design for an 8T EX-OR-NOR cell with full rail-to-rail output swing has been proposed. The proposed EX-OR-NOR cell is based on the hybrid circuit utilizing CMOS inverter and transmission gate logics, which thereby uses less power and minimizes propagation delay. Thus, a high-speed N-bit digital comparator design is accomplished using the proposed 8T EX-OR-NOR cell. In the present work 4-bit to 32-bit digital comparators are designed and implemented using the proposed circuitry. All the circuits are designed using Cadence electronic design automation (EDA) Virtuoso Design Environment for 180nm CMOS technology node. The outcomes are evaluated and verified with the comparator designs reported in the literature. The proposed modified N-bit digital comparators provide an excellent combination of speed, power consumption, and accuracy, making them a promising solution for modern digital electronics systems. [ABSTRACT FROM AUTHOR]

This paper presents the design of a comparator with low power, low offset voltage, high resolution, and rapid speed. The designed comparator is built on 45nm flip CMOS technology and runs 4.2G samples per second at nominal voltage. It is a custom-made comparator for a highly linear 4-bit Flash A/D Converter (ADC). The outlined design can operate on a nominal supply of 1.8 V. The comparator offset voltage was elevated because of this mismatch. To compensate for the offset voltage, we followed a decent approach to design the circuits. Therefore, the offset voltage is reduced to 250 uv. The designed comparator has a unity gain bandwidth of 4.2 GHz and a gain of 72db at nominal PVT, which gives us a considerable measure of authority. The dynamic power consumption of the comparator is 48.7uW. The layout of this designed comparator has been implemented, and the area of the comparator is 12.3umx15.75um. The results of pre-and post-layout simulations in various process, voltage, and temperature corners are shown. [ABSTRACT FROM AUTHOR]

In this study, we are going to design all optical 1-bit comparator by combining wave interference and threshold switching methods. The final structure composed of two nonlinear ring resonators and seven waveguides. The functionality of the suggested logical structure is analyzed and simulated by using plane wave expansion (PWE) and finite difference time domain (FDTD) methods. According to results, the proposed all optical 1-bit comparator has faster response and smaller footprint than all previous works. The maximum ON-OFF contrast ratio, delay time and area of the suggested optical comparator are about 16.67 dB, 1.8 ps, and 513 µm2, respectively. [ABSTRACT FROM AUTHOR]

Digital Circuits applications are expanding rapidly in modern times because they generate correct signals without errors or interferences. These digital circuits play important roles in data storage operation, as well as the implementation of image processing applications on hardware where the power, speed, and area of an electronic device play a significant role, particularly in the field of modern VLSI technology. The digital comparator with more number of bits plays an important role in image processing applications. In the proposed research paper, an attempt is made to design a speed and area efficient 32-bit comparator. To improve the speed of the comparator a modified priority encoder technique is used. It shows that the area of proposed 32-bit digital comparator consumes 573.73 units which are 20% better than when compared with the conventional comparators and the speed improved by 50% when compared with the Conventional Comparators. The proposed implementation is simulated on the 'Encounter(R) RTL Compiler RC14.28'. [ABSTRACT FROM AUTHOR]

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V. [ABSTRACT FROM AUTHOR]

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC. The dynamic comparator is customized to be simple in terms of the number of transistors to gain the advantage of low power and is also designed to have a low dynamic offset voltage. The stacking concept is embedded in the bit-slice unit of SAR logic to achieve reduced leakage power. This paper is concerned with how to contribute to low power consumption in all the aspects possible related to the implementation of the SAR ADC. With a 0.4 V supply and at 2 kS/s, the proposed ADC achieves an SNDR of 52.52 dB and a power consumption of 5.29 nW, resulting in a figure of merit (FOM) of 7.66 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works. [ABSTRACT FROM AUTHOR]

Research on artificial neural network computing based on conventional integrated circuit chips has made significant progress, but it faces technical bottlenecks such as reduced energy consumption, computing speed, and efficiency. So, it is seeking integrated chips based on optical interconnections to solve the current dilemma. Fortunately, the small size and very localized graphene surface plasmon waves offer the possibility of optical integrated chips. In this paper, we propose a graphene-based one-bit optical numerical comparator. The comparator is located on the top of a 0.4-μm2 rectangular dielectric layer, mainly consisting of Y-shaped graphene nanoribbons. The on/off effect of the graphene nanoribbons is achieved by applying an external voltage to change the chemical potential energy of the graphene switching bands. The proposed optical numerical comparator with 9.55-μm TM mode light achieves a minimum extinction ratio of 31.12 dB and amplitude modulation of 0.77 dB, as shown by the finite-difference time-domain (FDTD) method. Compared with the current optical numerical comparators, it has the advantages of a high extinction ratio, small size, low loss, and high stability. In addition, the effect of process deviation of graphene nanoribbons on the reliability of the designed optical numerical comparator is analyzed by simulation. It is beneficial to developing integrated photonic devices and has some significance for developing ultra-high-frequency and integrating artificial neural network computing. [ABSTRACT FROM AUTHOR]

In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effective in finding near-optimal solutions, it has not been extensively applied to the field of analog circuit design. Hence, this paper proposes a method to utilize GA in the optimization of a widely used circuit topology, namely the comparator. The comparator is considered the fundamental block in the design of most analog-to-digital converters (ADCs). For high-speed ADCs, dynamic comparators are usually chosen for the purpose of high speed and power efficiency. In summary, this paper introduces an innovative GA-Spectre architecture to optimize the dynamic comparator with respect to delay and power consumption. The post-optimized results are optimistic with a 72.61 ps delay and 3.11 µW power dissipation. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

High-precision, continuous analog comparators are widely used in signal detection, alarm protection, and other fields. An auto offset calibration method for high-resolution continuous CMOS comparators (CMPs) was proposed. On the basis of the first output of the short-input format CMP, calibration logic will select the proper routine to calculate the best fix trim bit. Two calibration codes are added and averaged to obtain the actual code. This mainly takes into account the fact that there may be a certain delay in comparator flipping, which leads to deviations from the optimal calibration code. This part of the search error can be counteracted by averaging the results of searching from low to high and from high to low. According to different design needs, different trim step sizes can be obtained by adjusting the relative ratio of the smallest calibratio N-channel metal-oxide-semiconductor (NMOS) to the main input pair. Circuit implementation is based on the 110 nm flash process with a 5 V IO device. Analysis and simulation results show that a less than 1 mV offset can be easily achieved, which is suitable for commercial use. The proposed auto offset calibration method does not increase current consumption and can be easily shifted to other advanced technology processes, which make it promising for future use. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μ W power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance. • Analysis of offset source of differential pairs. • Optimize comparator design. • Validate the comparator design. [ABSTRACT FROM AUTHOR]

The power optimization is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application. This logic has wide applications in the communication, nanotechnology, digital signal processing, computer graphics, optical computing, etc. In this paper, some proposed reversible magnitude comparator has been designed using the prevailing reversible gates and implemented using gate diffusion input (GDI) technique. The design methodologies are also proposed for the designing of N-bit comparator. The main objective of this paper is to design and implementation of reversible magnitude comparator using some proposed methods and compares them with the existing circuits in terms of constant input, garbage output, number of reversible gates, and quantum cost. The transistor implementations of the proposed comparators are done by the combination of CMOS and GDI technique in EDA Tanner tools. After the design and analysis of proposed comparators it has been found that the proposed-2 logic based 4-bit comparator has lowest quantum cost which is equal to 38 and the proposed-3 logic based 4-bit comparator has lowest constant input and garbage output which is equal to 8 and 13. [ABSTRACT FROM AUTHOR]

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra‐nanoscale region. Circuit designers explore a new technology for the ultra‐nanoscale region, which is the quantum‐dot cellular automata (QCA). Low‐energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low‐complexity, QCA‐based one‐bit digital comparator circuit for the ultra‐nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer‐E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design. [ABSTRACT FROM AUTHOR]

In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors' gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low V D D . Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at V D D = 0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at V i d = 1 mV. [ABSTRACT FROM AUTHOR]

A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output offset storage (IOS/OOS) and an offset trimming circuit was employed to reduce the offset of the cascade preamplifier and the operational transconductance amplifier (OTA), a novel offset trimming circuit with a 5-bit digital controller was designed to further reduce the residual offset voltage, and an improved self-calibration technology was also implemented to compensate the conversion error in SAR ADC system to a minimum. Simulation and measured results show that the input-referred offset calibrating range is ±9.15 mV at 0.61 mV/step, the low-voltage detection of SAR ADC is realized by compensating the conversion error to a minimum, and the effective number of bits (ENOB) and figure of merit (FoM) at 5 V supply and 2.5 M/s rate in the 12-bit SAR ADC with a 95 nm CMOS are 11.33 bits and 726.6 fJ/conversion-step, respectively. The proposed self-calibration comparator applied in the SAR ADC system can automatically eliminate the offset voltage caused by nonidealities and meet the requirements of the touch MCU. [ABSTRACT FROM AUTHOR]

RRAM devices have recently seen wide-spread adoption into applications such as neural networks and storage elements since their inherent non-volatility and multi-bit-capability renders them a possible candidate for mitigating the von-Neumann bottleneck. Researchers often face difficulties when developing edge devices, since dealing with sensors detecting parameters such as humidity or temperature often requires large and power-consuming ADCs. We propose a possible mitigation, namely using a RRAM device in combination with a comparator circuit to form a basic block for threshold detection. This can be expanded towards programmable non-uniform sampling ADCs, significantly reducing both area and power consumption since significantly smaller bit-resolutions are required. We demonstrate how a comparator circuit designed in 130 nm technology can be reprogrammed by programming the incorporated RRAM device. Our proposed building block consumes 83 µW. [ABSTRACT FROM AUTHOR]

This paper presents a new low-power, high-speed double-tail dynamic latched comparator with a novel pre-amplifier stage using peaking techniques approach in the design structure. Peaking is achieved for high frequency applications by connecting a negative capacitance in parallel with the output load capacitance of the pre-amplifier stage. Here, the negative capacitance can be realized by using a negative impedance converter (NIC) based on a cross-coupled nMOS latch circuit. This allows, to tune out surplus load capacitance and the bandwidth can be extended in the frequency domain. Consequently, both power consumption and delay time are reduced, the proposed circuit is designed in Ansys Electronics Suite and simulated with HSPICE using 65 nm TSMC technology node. For 1 V of supply voltage, at a clock frequency of 18 GHz with a differential input voltage (Δ Vin) of 25 mV, the simulation results reveal that the delay and average power consumption of the proposed dynamic comparator are 13.16 ps and 241 μ W respectively with 3.18fJ as energy per comparison. [ABSTRACT FROM AUTHOR]

Localized data conversions for sensors placed under harsh environmental conditions often require Analog to Digital Converters (ADC) capable of working under wide operating temperature range. Even though the fastest analog to digital converter, flash ADC is omitted from the high temperature regime due to the requirements of reference voltage source, reference voltage divider and a comparator array capable of providing stable operation under wide operating temperatures. A CMOS Schmitt inverter-based internal reference comparator array for flash ADC which is efficient in terms of area and power consumption, capable of working under wide temperature range is presented in this paper. The proposed idea replaces the reference voltage source, resistive reference voltage divider and differential comparator array of a conventional flash ADC by an array of suitably sized Schmitt inverters. The circuit was simulated for static and dynamic characteristics with gpdk 180 nm library using cadence virtuoso simulation suite. The voltage transfer characteristic curve (VTC) of the proposed comparator array was found invariable when a temperature sweep in the range of −40 to 170 degree Celsius was performed. Each of the comparator in the proposed array consumes a silicon area of 40.68 u m 2 and the average dynamic power consumption per cycle is estimated as 103.1 uW. [ABSTRACT FROM AUTHOR]

Background: Time-related bias can lead to misleading conclusions. Properly setting the "time zero" of follow-up is crucial for avoiding these biases. However, the time-zero setting is challenging when comparing users and non-users of a study drug because the latter do not have a time point for starting treatment. Objective: This methodological study aimed to illustrate the impact of different time-zero settings on effect estimates in a comparative effectiveness study using real-world data with a non-user comparator. Methods: Data for type 2 diabetes patients were extracted from an administrative claims database, and the onset of diabetic retinopathy (study outcome) was compared between users (treatment group) and non-users (non-use group) of lipid-lowering agents. We applied six time-zero settings to the same dataset. The adjusted hazard ratio (HR) for the outcome was estimated using a Cox regression model in each time-zero setting, and the obtained results were compared among the settings. Results: Of the six settings, three (study entry date [SED] vs SED [naïve approach], treatment initiation [TI] vs SED, TI vs Matched [random order]) showed that the treatment had a reduced risk of the outcome (HR [95% CI]: 0.65 [0.61–0.69], 0.92 [0.86–0.97], and 0.76 [0.71–0.82], respectively), one (TI vs Random) had an increased risk (HR [95% CI]: 1.52 [1.40–1.64]) , and two (SED vs SED [cloning method], and TI vs Matched [systematic order]) had neither increased nor decreased risk (HR [95% CI]: 0.95 [0.93–1.13], and 0.99 [0.93–1.07], respectively). Conclusions: This study demonstrates that different time-zero settings can lead to different conclusions, even if the same dataset is analyzed for the same research question, probably because improper settings can introduce bias. To minimize such biases, researchers should carefully define time zero, particularly when designing a non-user comparator study using real-world data. [ABSTRACT FROM AUTHOR]

This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications. [ABSTRACT FROM AUTHOR]

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it. [ABSTRACT FROM AUTHOR]

In this paper, a modified successive-approximation-register analog-to-digital converter (SAR ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. Also, by custom design for unit capacitor in the SAR ADC, the area has been reduced by 46% compared to the conventional structure. The proposed ADC with a sampling frequency of 1 kS/s and power consumption of only 1.21 nW for biomedical applications has been designed and simulated in a TSMC 65 nm CMOS technology and occupies an area of 0.013 m m 2. The proposed biomedical ADC is verified using analog electroencephalogram (EEG) and electrocardiogram (ECG) inputs which demonstrate it is proper to quantize these biosignals. The figure-of-merit (FOM) of the proposed converter is 3.2 fJ/conversion-step. • Designing a modified ADC with an ultra low supply voltage (0.2 V) for biosignals acquisition. • Designing a novel 0.2 V, ultra low power dynamic comparator. • The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. • 46% reduction of occupied area using custom capacitor design. [ABSTRACT FROM AUTHOR]

Comparator plays a vital role in many IC applications, Microprocessors, computer systems etc. Hence it is desirable to design a comparator block with low power consumption and high speed performance. In this paper a novel architecture of 32-bit comparator using Complementary metal-oxide semiconductor logic is proposed and computed its delay and power metrics. Further it is compared with the full adder based 32-bit comparator. From the analysis we derive the comparison between proposed and the conventional comparator. The complete designing of architectures and their result analysis was done in cadence virtuoso tool at 180 nm technology. Simulation results show that there is reduce in power consumption of 90% when compared to the conventional full adder based comparator. [ABSTRACT FROM AUTHOR]

This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results. [ABSTRACT FROM AUTHOR]

This paper presents novel high speed low power comparator that can further be used in analog to digital converter (ADC) circuits for Internet of Things (IoT) applications. Both circuits employ self cascode technique in preamplifier stage of conventional comparator. The proposed comparator 1 uses a static latch in second stage whilst dynamic latch is used as second stage in proposed comparator 2 to take advantage of low power. Simulations are carried out at 90 nm CMOS technology node in Cadence Virtuoso environment. Self cascode preamplifier stage shows better gain (40 %) than conventional counterpart leading to improvement of 45 % in power with 65 % lesser delay. The mathematical formulation of the delay of proposed comparators is also put forward. Post layout simulation results for delay, power, energy and area of proposed comparator 1 are observed to be 110 ps, 65uW 78fJ/conversion energy and 151um2 respectively. The corresponding data for proposed comparator 2 is 81 ps, 61uW, 56 fJ/conversion energy and 137um2. These results are found to be in much better proposition than other state-of-the-art works. Additionally, the performance of conventional and proposed comparators is examined using Monte-Carlo simulations and corner analysis. The proposed comparators outperform under these analyses also. [ABSTRACT FROM AUTHOR]