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The increasing complexity of modern superconductive circuits, and single flux quantum (SFQ) circuits in particular has made the issue of flux trapping of growing importance. The use of wide superconductive striplines for signal routing has exacerbated this issue. Trapping residual magnetic fields in these striplines degrades performance while reducing margins, damaging the operability of superconductive circuits. In this article, an area efficient topology for striplines is introduced to manage flux trapping in large scale SFQ circuits. This topology is composed of narrow parallel lines in series with small resistors. The proposed topology decreases the length of the striplines by exploiting the mutual inductance between the narrow parallel lines. The topology requires significantly less area while preventing flux trapping within wide superconductive striplines. The narrow parallel line topology also reduces coupling capacitance between striplines. The proposed approach is compatible with automated routing of large scale SFQ integrated circuits. [ABSTRACT FROM AUTHOR]

Inductance in superconductive circuits plays a significant role in rapid single flux quantum (RSFQ) systems. Inductance estimation is a challenging issue. The microwave behavior of these inductances is characterized by the surface inductance of a line. A methodology to accurately estimate the surface inductance of a stripline is the focus of this brief. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is provided. The effects of process parameter variations on the surface inductance are also discussed. An expression to model the effects of the trapezoidal geometry of a stripline is presented. The dependence of the surface inductance on the oxide and metal layer thicknesses is also presented. The objective is to provide an accurate estimate of the surface inductance for use in automated routing of VLSI complexity RSFQ circuits. [ABSTRACT FROM AUTHOR]

Considering the two main categories of rapid single flux quantum gates with destructive and nondestructive readout process, we have investigated the effects of readout cell topology and involved critical parameters on the proper functionality and stability of the states of the newly developed bidirectional T flip-flops (TFFs). It is observed that instabilities and fluctuations in the state of the gate (memory of TFF) after each transition determine the minimum time intervals between the clock pulses set by the ac bias current, further limiting the ultimate operation frequency of the circuits. The absolute values of the current levels of the junctions at each state, which play an important role in the behavior of the cell, are studied, and their variations over several consequent pulses are stabilized by optimizing the cell parameters. The appropriate values of the circuit and junction parameters are found, resulting in the optimum operation of the circuit for having the best margins possible. We report on the investigated circuit topology and parameter optimizations of the readout circuit of the considered bidirectional TFF. [ABSTRACT FROM PUBLISHER]