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Research was conducted to examine the manufacturability of superconductor-based computation modules including the integrated circuit foundry process, packaging and data link out of the cryopackage. The study focused on the critical technical challenges that exist in each of the areas. A technology roadmap aimed at achieving the Hybrid Technology Multi-threaded requirements is presented.

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses ac power carried on a transmission line, which also serves as a clock. Using simple experiments, we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins, and a low bit-error rate. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of single-flux-quantum signals with the design methodology of semiconductor digital logic, including low static power dissipation, low latency combinational logic, and efficient device count. [ABSTRACT FROM AUTHOR]

High performance oversampling Delta-Sigma data converters require high clock rates and accurate feedback of the digital output to the analog regime. Superconductor modulators offer the unique advantages of clock rates in the tens-of-gigahertz, comparator switching energy below attoJoules, and quantum-ac. curate digital-to-analog feedback. We have designed a two-loop baseband modulator whose noise transfer function was calculated using a simple, linear circuit model. The circuit was fabricated in a commercial superconductor IC process with 4.5 kA-per-square cm Josephson junctions and 1.5 micron minimum feature size. The circuit was tested at a derated sample rate of 5 GHz. Measured signal-to-noise dynamic range was 81 dB over a 10 MHz band. Third-order intercept was measured to be +24 dBsat in two-tone test. The measured noise transfer function was in excel- lent agreement with our linear model. The linear model indicates that with appropriate parameter values, this family of modulators extrapolates to significantly higher performance. [ABSTRACT FROM AUTHOR]

Superconductor Delta-Sigma modulators feature quantum accurate feedback that allows them to operate in the ideal, quantization-noise limit. We have developed a linear model that predicts the quantization noise of the modulator analytically, by mapping the white quantization noise at the comparator to frequency-dependent noise at the output. The key advance was determination of the trans impedance of the Josephson comparator. Both first order modulators, such as the phase modulation/demodulation design, and our own second order modulator have been analysed. We conclude that first order modulators all have the same noise shaping performance irrespective of circuit parameter values and feedback gain. The primary constraint on circuit design is instead set by thermal noise considerations. [ABSTRACT FROM AUTHOR]

A suitable dab link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall lime and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA/cm² foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of ± 21 % on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation. [ABSTRACT FROM AUTHOR]

We recently reported communication up to 60Gb/s between digital superconductor chips mounted on a passive carrier, using a novel driver circuit that produces a double-flux-quantum pulse. Here, we answer various practical questions pertaining to chip-to-chip and on-chip communication in greater detail. On-chip, the traditional single-flux-quantum driver is adequate, although margins and bit error rate degrade significantly at the microstrip resonance frequency. Chip-to-chip, using the double-flux-quantum driver, shows little frequency dependence, in spite of 13% reduction of signal current in the chip-to-chip transitions. Appropriate microstrip impedance is in the range 4-8 Ω for a 4kA/cm² Josephson junction IC process. Data includes bit errors rates for pseudo-random data in the range 3-27 Gb/s. [ABSTRACT FROM AUTHOR]

The bias current requirement for RSFQ circuits is about an ampere per thousand gates. High current increases the thermal load of cables into the cryostat, produces undesirable currents and fields on-chip, and makes efficient power supply difficult. Series-biasing has been proposed, whereby the circuit is divided into blocks powered in series. This requires floating ground planes for each block, and differential signal propagation across ground plane boundaries where the blocks communicate. We have demonstrated transmission of pseudo-random data across a differential link using two distinct approaches, based on magnetic and capacitive coupling. For each circuit, we have measured data rates up to 30 Gb/s and bit error rates down to 10[sup -10]. Bit error rates extrapolate to lower values. Inductive coupling was implemented in TRW's 4 kA/cm² Nb process, capacitive coupling in TRW's 8 kA/cm² process. [ABSTRACT FROM AUTHOR]

Describes a single flux quantum (SFQ) superconductor circuit concept that mimics complementary metal oxide semiconductors to achieve ultra-low power dissipation and ultra-high clock rates. Traditional approach to superconductor digital circuits; Evolution of the self-clocked, complementary logic concept; Future SFQ circuit implementations.

Examines a process technology that allows an increase in superconductor integrated circuit speed and density. Reduction of critical dimension variation and improvement in linearity; Minimum junction diameter and contact; Electrical performance.

Examines wide bandwidth oscillator/counter analog-to-digital converters implemented in superconducting electronics. Architecture; Scalability; Conversion process; Power dissipation; Theoretical performance.

Discusses the effect of temperature on the bit error rate (BER) of a clocked superconducting digital circuit. Effect of control current on BER; Fokker-Planck equation to model comparator dynamics.

Compares the bit-error rate of an active Single Flux Quantum (SFQ) experiment to theorectical prediction. Development of the theory of thermally induced errors using the Fokker-Planck equation; Equivalent noise temperature of the experiment.

Reciprocal quantum logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2 GHz. Latency is only 150 ps at a clock rate of 10 GHz. [ABSTRACT FROM AUTHOR]

Superconductor digital devices using single-flux-quantum (SFQ) data encoding offer higher speed at lower power than any other integrated circuit technology. For this very reason, interconnect is challenging. We report SFQ data transfer between chips flip chip mounted on a passive microstrip carrier. The flip-chip structure achieves bandwidths greater than 250 GHz. Unlike previous designs, our signal lines are terminated at both ends; this is accomplished using a driver that produces a double-flux-quantum signal. We measured the circuit for pseudorandom data in the range of 10–60 Gb/s. Bit error rates are measured down to 1E-10 and extrapolate to negligible values. The signal power on the microstrip is only 30 nW at 60 Gb ps. © 2002 American Institute of Physics. [ABSTRACT FROM AUTHOR]