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In this letter, a new rail‐to‐rail two‐stage regenerative comparator for low supply voltage applications is presented. A rail‐to‐rail operation is achieved by utilizing an inverse inverter pre‐amplifier. The proposed comparator is post‐layout simulated within a standard 180‐nm CMOS technology. In the worst‐case scenario, the energy efficiency and the delay of the comparator are improved by more than 80% compared to the conventional single‐stage comparator. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed common-mode insensitive two-stage regenerative comparator designed for low supply voltage applications. The proposed comparator features a doubled transistor latch that enables rail-to-rail operation, which is pioneered to the best of the author's knowledge. The voltage swing of output nodes of the pre-amplifiers is limited to reduce the power consumption. This limitation boosts the regeneration speed of the doubled transistor latch. The proposed comparator realized by a standard 65 nm CMOS technology. The post-layout simulation results corroborate that the proposed comparator with 50 MHz sample rate and 0.6 V supply voltage dissipates 3.4 µW power, and occupies 168 µm2 area. Also, the offset voltage variation within the full common-mode range can be below 2 mV. In a worst-case scenario compared to the conventional single-stage comparator, the proposed comparator improves delay and energy efficiency by more than 80%. Considering its overall performance, this energy-efficient comparator is suitable for all low supply voltage applications, including Internet of Things (IoT), successive approximation registers analog-to-digital converters (SAR ADCs), and biomedical implants. [ABSTRACT FROM AUTHOR]