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Thinning the buffer layer thickness between the GaN epilayer and Si substrate without introducing large residual stress is persistently desired for GaN-on-Si devices to promote their thermal budgets and low-cost, multifunctional applications. In this work, the GaN-on-Si heterostructures were directly bonded at room temperature by surface activated bonding (SAB) and the therein residual stress states were investigated by confocal micro-Raman. The effects of thermal annealing process on the residual stress and interfacial microstructure in SAB fabricated GaN-on-Si heterostructures were also systematically investigated by in situ micro-Raman and transmission electron microscopy. It was found that a significant relaxation and a more uniform stress distribution was obtained in SAB bonded GaN-on-Si heterostructure in comparison with that of MOCVD grown sample; however, with increasing annealing temperature, the residual stresses at the SAB bonded GaN layer and Si layer evolute monotonically in different trends. The main reason can be ascribed to the amorphous layer formed at the bonding interface, which played a critical stress relaxation role and transformed into a much thinner crystallized interlayer without any observable structural defects after 1000 °C annealing. [ABSTRACT FROM AUTHOR]

Recent achievements in the research of heterojunctions fabricated using surface activated bonding (SAB), one of the practically useful direct wafer bonding technologies, are discussed. The response of bonding interfaces to post-bonding annealing is focused. These junctions reveal high thermal tolerance (1000 °C in the case of junctions made of widegap materials) despite differences in coefficients of thermal expansion between bonded materials. Defect layers with several nm thickness formed by the surface activation process at the as-bonded interfaces get faint and their electrical and mechanical properties are improved by annealing. These results show that as-bonded interfaces are in a metastable state, and novel functional devices are likely to be realized by applying wafer processing steps to SAB-based junctions. Characteristics of IIIâ€"V//Si multijunction solar cells, GaN-on-diamond high electron mobility transistors, and metal-foil based low-loss interconnects that are fabricated by processing SAB-based junctions are described, and future prospects are presented. [ABSTRACT FROM AUTHOR]

Coplanar waveguides (CPWs) are fabricated by directly bonding 17 μ m Al foils to Si substrates with different resistivities and wet etching. Their RF characteristics are compared with those of CPWs fabricated on 0.8 μ m thick evaporated Al layers. A lower insertion loss is observed for Si substrates with higher resistivity irrespective of the thickness of conductors because the substrate loss is decreased. For a 10000-Ω · cm Si substrate, Al-foil-based CPWs reveal a ∼0.7 dB cm−1 lower insertion loss in comparison with evaporated-Al-based CPWs at 1 GHz. These features agree with the calculation, which implies the superiority of direct bonding of metal foils for realizing low-loss passive components. [ABSTRACT FROM AUTHOR]

Chemical composition around diamond/silicon heterointerfaces fabricated by surface activated bonding (SAB) at room temperature is examined by energy-dispersive X-ray spectroscopy under scanning transmission electron microscopy. Iron impurities segregate just on the bonding interfaces, while oxygen impurities segregate off the bonding interfaces in the silicon side by 3–4 nm. Oxygen atoms would segregate so as to avoid the amorphous compound with silicon and carbon atoms, self-organized at the bonding interfaces in the SAB process. When the bonding interfaces are annealed at 1000 °C, the amorphous compound converts into cubic silicon carbide (c-SiC), and nano-voids 5–15 nm in size are formed at the region between silicon and c-SiC, at which the oxygen density is high before annealing. The nano-voids can act as the gettering sites in which metal impurities are preferentially agglomerated, and the impurity gettering would help to improve the electronic properties of the bonding interfaces by annealing. [ABSTRACT FROM AUTHOR]

We fabricate AlGaN/GaN high electron mobility transistors (HEMTs) on diamond substrates by transferring 8 μ m heterostructures grown on 3C-SiC/Si templates and subsequently applying the conventional device process steps. No exfoliation of 3C-SiC/diamond bonding interfaces is observed during 800 °C annealing, the essential step for forming ohmic contacts on nitrides. The thermal resistance of HEMTs on diamond is 35% of that of HEMTs on Si, which is assumed to be the origin of smaller negative drain conductance in on-diamond HEMTs. The results imply that the bonding-first process is applicable for fabricating low-thermal-resistance HEMTs with thick nitride layers. [ABSTRACT FROM AUTHOR]

Abstract From transmission electron microscope (TEM) observation, a 25 nm thick amorphous layer was confirmed at the diamond/Si bonding interface without annealing, the amorphous layer thickness decreased with the annealing temperature. No cracking even in nanometer scale occurred even after high-temperature annealing at 800 °C. From in-situ micro-Raman monitoring, the compressed stress was observed in the Si of the bonding interface without annealing with respect to the bonding Si substrate. A tensile stress relaxation was observed in the diamond of the bonding interface with respect to the polished diamond. These results were attributed to the large load applied to the diamond and Si substrates during bonding process. After annealing at 400 °C, the residual stress in the Si of the bonding interface decreased, while the residual stress in the diamond of the bonding interface increased, which should be due to the residual stress caused by the applied load was released by annealing process. The residual stress in the Si and diamond of the bonding interface increased and decreased, respectively, as the annealing temperature increased from 400 to 1000 °C. The main reason was due to the structure change of the amorphous layer and the tensile stress relaxation in the diamond of the bonding interface. Graphical abstract Unlabelled Image Highlights • Diamond/Si bonding interface could withstand a load of high temperature as high as 800 °C. • The amorphous layer observed at the bonding interface decreased with annealing temperature. • The residual stress released in the diamond of the bonding interface decreased with annealing temperature. • The residual stress formed in the bonding interface annealed at 1000˚C is much smaller than that of diamond grown on Si. [ABSTRACT FROM AUTHOR]

Abstract Direct bonding of diamond and Al is achieved by surface activated bonding at room temperature. The interfacial structures of the diamond/Al bonding interface with annealing at different temperatures are investigated under in-situ annealing in a transmission electron microscope (TEM). An amorphous layer with a thickness of 4 ± 0.5 nm is formed at the bonding interface without annealing, the thickness of the amorphous layer decreases with increasing annealing temperature, the amorphous layer vanished after annealing at 600 °C. No structural defects are observed at the bonding interface with annealing at different temperatures. [ABSTRACT FROM AUTHOR]

Group-III nitride on Si tandem solar cell structures, which are free from materials with high impacts on the environment such as group-III arsenides or phosphides, were successfully fabricated using the surfaceactivated bonding of nitride-based sub cells, which had been grown on (0001) GaN substrates, and (111) Si-based sub cells. The backsides of the GaN substrates had been polished and their averaged roughness was smaller than 1 nm prior to bonding. The open-circuit voltage ( VOC) of the tandem cells was almost equal to the sum of VOC of the respective sub cells, while the conversion efficiency was limited by the properties of the nitride-based top cells. Nitride-on-(100) Si tandem cells were also fabricated and the enhancement in VOC was observed. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Highlights • A transition layer was formed at the interface by irradiation of Ar FAB. • The thickness of buried oxide at the interface was quantitatively estimated. • The interfaces were found to be in the meta-stable states. Abstract Hard X-ray photoelectron spectroscopy measurements are performed on ≈10-nm-thick GaAs film/Si substrate junctions fabricated by the surface activated bonding and selective wet etching. The chemical shifts of Ga O and As O signals in Ga 2p 3/2 and As 2p 3/2 core spectra indicate that oxides are formed in a part of GaAs films neighboring GaAs/Si interfaces due to the surface activation process. Analyses of Ga O and As O signals show that the thickness of such buried oxides is decreased due to a post-bonding annealing at temperatures up to 400 °C. This means that the electrical properties of bonding interfaces, which are in the meta-stable states, are improved by the annealing. The thickness of oxides is different from that of amorphous-like transition layers at the GaAs/Si interfaces observed by transmission electron microscopy. [ABSTRACT FROM AUTHOR]

We evaluated the current–voltage (I-V) and temperature-dependent I-V characteristics of n+-Si/p-diamond heterojunction diodes (HDs) fabricated by using surface activated bonding and Ru/p-diamond Schottky barrier diodes (SBDs). Both types of diodes were fabricated on diamond surface that was activated using a fast atom beam of Ar. Their room-temperature reverse-bias characteristics were explained using the trap-assisted tunneling model, wherein the surface activation process affects the carrier transport across the Si/diamond and Ru/diamond interfaces. In addition, we compared the electrical properties of n+-Si/p-diamond HDs and Ru/p-diamond SBDs with those of previously fabricated p+-Si/p-diamond HDs and Al/p-diamond SBDs. A correlation between the barrier heights and the work function of the contact materials (n+-Si, p+-Si, and Ru) was observed. [Display omitted] • We fabricated n+-Si/p-diamond heterojunction diodes (HDs), and demonstrated their diode characteristics. • The reverse-bias characteristics of HDs were explained by the trap-assisted tunneling model. • The S factors of Si/diamond and Ru/diamond interfaces was as high as ≈0.7 after annealing at 703 K. • The partially "pinning-free" interfaces were formed thank to Ar beam irradiation. [ABSTRACT FROM AUTHOR]

We fabricate p+-Si/p-diamond heterojunction diodes by using surface-activated bonding and examine the electrical properties of Si/diamond interfaces by measuring current-voltage and current-voltage-temperature characteristics. We find that the electrical properties of heterojunction diodes are improved by post-bonding annealing at temperatures up to 873 K in terms of the ideality factor and reverse-bias current. Additionally, fabricated diodes also reveal thermal stability better than that of Cu/diamond Schottky diodes in terms of the rectification factor. The barrier height at Si/diamond bonding interfaces annealed at 873 K is estimated to be 0.55 and 0.66 eV by analyzing the relationship between the saturation current density and temperature and the reverse-bias characteristics at room temperature, respectively. These values are close to that obtained by assuming that no offset is formed in the vacuum level across the Si/diamond bonding interfaces (0.36 eV). [Display omitted] • We fabricated p+-Si/p-diamond heterojunction diodes using surface-activated bonding and demonstrated their characteristics. • The characteristics of Si/diamond heterojunction diodes were improved by means of the post-bonding annealing. • A high therm al stability of Si/diamond heterojunction diodes was shown. • The band lineup across the Si/diamond bonding interfaces was extracted from measurements. [ABSTRACT FROM AUTHOR]

By using the sacrificial layer (SL) etching, GaAs substrates are separated from III–V epi substrate//Si substrate junctions that are made by surface activated bonding (SAB) technologies. The post-bonding low-temperature (300- ∘ C) annealing plays an essential role in achieving a promising (∼ 90%) bonding yield. The effects of the post-bonding annealing are investigated by hard X-ray photoemission spectroscopy and current–voltage measurements of GaAs//Si bonding interfaces. It is found that the concentration of oxygen atoms at interfaces is reduced and the resistance decreases to 1.6–2.1 m Ω cm 2 by the low-temperature annealing. Aluminum fluoride complexes are not observed by X-ray photoelectron spectroscopy on the exposed surfaces of separated GaAs substrates. The roughness average of the surfaces is ≈ 0.25–0.30 nm. The characteristics of double junction cells fabricated on the GaAs//Si junctions prepared by the SL etching are almost the same as those of cells fabricated by dissolving GaAs substrates after bonding. These results indicate that multijunction cells could be fabricated in a process sequence compatible with reuse of GaAs substrates by combining the SL etching and SAB. • III–V//Si junctions with a ∼ 90% of bonding yield is achieved in III–V//Si junctions prepared by direct wafer bonding and subsequent epitaxial lift-off. • A post-bonding annealing plays an essential role in realizing interfaces with an enough tolerance against HF-based solution for sacrificial layer etching. • The epitaxial lift-off process causes no influence on performances of MJ cells. [ABSTRACT FROM AUTHOR]