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Purpose: The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model. Design/methodology/approach: The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy. Findings: The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. Ion/Iambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs. Originality/value: The modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach. [ABSTRACT FROM AUTHOR]

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple-material double-gate (DG) metal-oxide-semiconductor field-effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple-material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short-channel effects is evaluated by comparing the relative performance parameters such as drain-induced barrier lowering, threshold voltage roll-off, and subthreshold swing with its counterparts in the single-material DG and double-material DG metal-oxide-semiconductor field-effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate-engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum-mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The paper presents a model for subthreshold surface potential and threshold voltage for a Double Halo Dual Material Gate (DHDMG) MOSFET. A pseudo-2D analysis applying Gauss law along the surface is used to model the subthreshold surface potential. The same model is used to find out the threshold voltage for Gaussian profile-based DHDMG. The proposed model is derived based on two Gaussian pileup profiles located at the source and drain ends of a MOSFET. The model has a simple compact form that can be utilized to characterize the advanced halo-implant MOSFETs. The model is also applied to find out the surface potential using high-k gate dielectric materials. The model is verified against 2D device simulator DESSIS. The simulation results show that the model predicts the value of the threshold voltage fairly accurately for the different devices and pocket parameters along with various bias voltages. [ABSTRACT FROM AUTHOR]

SUMMARY This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket-implanted Double-Halo Dual-Material Gate (DHDMG) and Single-Halo Dual-Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual-material gate) to effectively suppress the short-channel effects (SCEs). The model is derived using the pseudo-2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual-material gate with single-halo and double-halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll-off than a pocket-implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

An analytical subthreshold surface potential model for short channel, LAC, double halo and DMG MOSFETs, including the effect of inner fringing field, is presented, considering the surface potential variation with the depth of the channel depletion layer. Gauss's law is applied to a box. The inner fringing field capacitances at the two ends of the MOSFET become prominent with the shrinking of device dimension which are considered in our model for perfect estimation of subthreshold surface potential. The model is verified against 2D device simulator DESSIS. [ABSTRACT FROM AUTHOR]

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal-oxide-semiconductor field-effect transistor) operating up to 40 nm regime. The model is derived by applying Gauss's law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs. [ABSTRACT FROM AUTHOR]

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new two-dimensional (2-D) analytical model of dual material junctionless surrounding gate MOSFET (DMJLSRG MOSFET). The expressions of potential and Electric Field of the gate engineered MOSFET structure have been obtained by solving the 2-D Poisson’s equation in subthreshold regime using a parabolic potential approximation considering effective conduction path effect (ECPE). The developed potential model accurately predicts the perceivable step function in the potential profile, responsible for effective screening of the drain potential variation in order to reduce DIBL and threshold voltage roll-off. In this work, effectiveness of dual material gate engineered (DM) design for junctionless MOSFET was scrutinized by comparing the results with a single material gate junctionless surrounding gate MOSFET (SMJLSRG MOSFET) of same dimension. From the developed potential model, a simple and accurate analytical expression of threshold voltage is also derived. Results reveal that DMJLSRG devices offer superior performance as compared to SMJLSRG devices. An improvement of hot-carrier effects (HCEs) and a reduction of short-channel effects (SCEs) have been demonstrated for gate-engineered DMJLDG device over the corresponding conventional (SMJLDG) device. The proposed model can be used as a basic design guideline for gate-engineered junctionless surrounding gate MOSFETs. [ABSTRACT FROM AUTHOR]