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An analytical surface-potential-based drain current model for amorphous indium–gallium–zinc–oxide (a-InGaZnO) thin film transistors (TFTs) is proposed by introducing an effective charge density approach in this paper. This approach gives two initial approximate values of the effective state density and the effective thermal voltage by using the dominant state of the free charge density in total charge density, and then obtains a high-precision one-exponent equivalent transformation for three-exponent total charge density. Based on this approach, we have solved the problem that the physical meaning of the transition area in the regional method is not clear and a one-piece analytical surface potential solution to Poisson's equation is successfully derived. Furthermore, the drain current is also explicitly derived from the charge sheet model and I-V characteristics of a-InGaZnO TFTs are reproduced from the above obtained model. Finally, accurate and effective surface-potential model and drain current model are obtained and verified by experimental data, respectively. Good verification results prove that the proposed model could become an accurate and suitable tool for being embedded into a circuit simulation. [ABSTRACT FROM AUTHOR]

Abstract A closed-form drain current compact model for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), including the influence from trapped charges, is presented in this paper. Accounting for both channel and interface trapped charges in this model, we explicitly solve the inherent closed-form surface potential by improving the computational efficiency of the effective charge density approach. Furthermore, based on the explicit solution of the surface potential, the expressions of the trapped and inversion charges in the channel film are derived analytically, and the drain current is integrated from the charge sheet model. Then, for the cases of the different operational voltages, the accuracy and practicability of our model are verified by numerical results of the surface potential and experimental data of the drain current in amorphous In-Ga-Zn-O TFTs, respectively. Finally, we give a discussion about the influence of the interface trapped charges on the device reliability. As a result, the model can be easily to explore the drain current behavior of the AOS TFTs for next-generation display circuit application. Highlights • An inherent closed-form trapped-charge-included drain current compact model of AOS TFTs is derived. • The closed-form surface potential without smoothing function is explicitly solved. • The drain current is derived from the charge-sheet model and validated by experimental data. • Some discussions are gave about the influence from interface trapped charges on the DC properties of AOS TFTs. [ABSTRACT FROM AUTHOR]

An analytical surface-potential-based drain current model of dynamic-depletion (DD) polysilicon (poly-Si) thin-film transistors (TFTs) is proposed in this paper. In the 1-D Poisson equation, total charge density is reformulated by an effective charge density, which allows a closed-form surface potential calculation scheme. Different boundary conditions between partial depletion and full depletion are calculated and unified into one back-gate potential in the DD mode, which allows a unified-form surface potential calculation scheme. Combining with Gauss’s theory, we explicitly solve a closed- and unified-form surface potential of DD poly-Si TFTs. Based on the solution of the surface potential, the drain current is derived analytically from the Pao–Sah integration. Furthermore, our solution is verified by numerical results and experimental data, respectively. As a result, such a model can accurately predict I–V characteristics of DD poly-Si TFTs and provide computational efficiency for TFT process optimization and circuit simulations. [ABSTRACT FROM AUTHOR]

We propose an explicit surface-potential-based direct current (dc) model for fully depleted polysilicon (poly-Si) thin-film transistors (TFTs). Being analytical and explicit, the proposed model is a solid base for compact models of these devices. The essential for our model is the explicit calculation of the surface potential, using the Lambert W function. Subsequently, using the surface potential, we also develop the expressions for charge and current, employing well established approaches, which include integration of carrier’s charge for drain current. Furthermore, the solutions of surface potential and drain current were validated by numerical results and experimental data, respectively. Finally, we discussed in detail about the effects on the surface potential and dc properties from the full depleted poly-Si TFT parameters. As a result, such a model is suitable to be implemented into computer-aided simulations of both device and circuit designs, due to its high computational accuracy and efficiency. [ABSTRACT FROM AUTHOR]

An analytical surface-potential-based drain current model of symmetric double-gate (sDG) MOSFETs is described as a SPICE compatible model in this paper. The continuous surface and central potentials from the accumulation to the strong inversion regions are solved from the 1-D Poisson’s equation in sDG MOSFETs. Furthermore, the drain current is derived from the charge sheet model as a function of the surface potential. Over a wide range of terminal voltages, doping concentrations, and device geometries, the surface potential calculation scheme and drain current model are verified by solving the 1-D Poisson’s equation based on the least square method and using the Silvaco Atlas simulation results and experimental data, respectively. Such a model can be adopted as a useful platform to develop the circuit simulator and provide the clear understanding of sDG MOSFET device physics. [ABSTRACT FROM AUTHOR]

A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal's experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10−7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal's experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations. [ABSTRACT FROM AUTHOR]