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Acquisition of the accurate phase currents is indispensable for the control and protection of switched reluctance motor (SRM) drives for electric transportation applications. Existing phase current reconstruction techniques for SRM are implemented under the current control techniques, which generate large torque pulsations. Therefore, the direct torque control (DTC) method can be adopted to minimize torque pulsations and to enhance transient performance in electrified vehicles. However, the existing current estimation methods cannot be applied to DTC strategies due to the simultaneous conduction of all phases at any switching instant. Furthermore, it offers a lower torque per ampere ($T/A$) ratio and draws a high source current. This article addresses the aforementioned concerns by proposing a cost-effective phase current reconstruction method with an improved DTC strategy for a 4-kW four-phase SRM drive. This method employs a 16-sector partition method with a new voltage vector selection by detecting zero-current regions of each phase. As a result, the long-tail currents can be avoided, thereby limiting the simultaneous conduction of all phases. The simulation and test results show that the proposed DTC has minimal torque pulsations, high $T/A$ ratio, low converter losses, and lower source current ripple in comparison to the existing DTC schemes under various operating conditions. Also, the proposed phase current estimation method effectively reconstructs the phase currents under both steady-state and transient operating conditions. [ABSTRACT FROM AUTHOR]

The series connection of low-power modules is an alternative solution to realize a multilevel inverter. Unlike a cascade connection, the series connection approach significantly reduces the number of isolated dc sources, thereby the design complexity, cabling of the transformer, and overall system cost become low. In this article, the operation of the series-connected multilevel inverter is presented for a five-level operation, and it is realized by using two three-level half-bridge diode clamp converter modules per phase. Hence, each phase of the series-connected multilevel inverter requires a single isolated dc source. In the series-connected multilevel inverter, the net dc-bus voltage will be equally distributed between four dc-bus capacitors. Therefore, the converter generates a multilevel voltage waveform with uniform steps and ensures equal voltage stress on the semiconductor devices. To achieve these objectives, a space vector pulsewidth modulation scheme with an additional voltage balancing approach is employed. The feasibility of series-connected multilevel inverter is validated through simulations and a scaled-down laboratory prototype under steady-state and transient conditions. [ABSTRACT FROM AUTHOR]

In this article, a new five-level voltage source inverter is proposed for high-power applications. The proposed inverter is competitive in performance, component count, and control complexity compared with the conventional multilevel inverters. Also, the proposed inverter has a simple structure as it does not have any dc-link neutral points, unlike hybrid converters. Furthermore, the proposed topology can be connected in a back-to-back due to the presence of a common dc-link. Also, there is no need of isolated dc source and a complex phase-shifting transformer. In addition, a simple voltage balancing approach based on a level-shifted carrier pulsewidth modulation scheme is proposed to control the flying capacitor voltages. The proposed approach will make use of the redundancy switching states to balance the flying capacitor voltages in the proposed inverter. The steady-state and transient performance of the proposed five-level voltage source inverter and voltage balancing approach is validated through MATLAB simulation studies at different power factors and modulation indices. The simulation studies are further evaluated experimentally by a scaled-down laboratory prototype. Furthermore, the feasibility of the proposed topology is analyzed under the performance indices of voltage and current harmonic distortion, flying capacitor voltage ripples, converter power losses, and converter efficiency. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge (CHB) is a promising topology for medium-voltage high-power applications. CHB consists of low-power H-bridge modules in each phase, and these modules are connected in a cascade manner to achieve multilevel operation. However, CHB requires a phase-shifting transformer with multiple secondary windings to generate an isolated dc source for each module, and this requirement increases the overall system cost. In this paper, a series connection of low-power modules is employed to realize a new power converter called a series-connected multilevel converter. Each phase of the proposed topology requires a single isolated dc source. Hence, the required number of secondary windings is considerably reduced. This approach also minimizes the complexity and cost of the overall system. The operation of the proposed topology is presented by using three-level neutral point clamped modules in each phase. Model predictive control (MPC) is employed to control the dc-bus capacitor voltage and output currents of the proposed topology. A discrete-time mathematical model of the proposed topology is also developed to predict the future behavior of control variables. The performance of the proposed topology with MPC is verified through MATLAB simulations and a scaled-down laboratory prototype. [ABSTRACT FROM AUTHOR]

The five-level nested neutral-point-clamped (5L-NNPC) converter is one of the most promising topologies for medium-voltage (2.3–7.2 kV) high-power applications such as medium-voltage drives, wind energy conversion systems, and grid-connected systems. The 5L-NNPC requires a fewer number of switching devices, freewheeling and clamping diodes, and flying capacitors compared to the existing five-level multilevel converters. In the 5L-NNPC topology, each flying capacitor voltage is regulated at one-fourth of the dc-bus voltage to obtain the five-level operation. Due to the lack of redundant switching states, it is difficult to control the flying capacitor voltages by using the pulse-width-modulation-based classical control methods. This paper proposes a model-predictive current control (MPCC) approach to control the flying capacitor voltages along with the output currents of the 5L-NNPC converter. The discrete-time model of 5L-NNPC is developed to implement the MPCC scheme. The simulation and experimental studies are conducted to verify the dynamic and steady-state performance of 5L-NNPC with the MPCC scheme. The performance of the proposed MPCC approach is compared with the conventional space-vector-modulation-based voltage-balancing approach. Furthermore, the flying capacitor voltage control capability of MPCC is verified at different load power factors. [ABSTRACT FROM AUTHOR]

The five-level modular neutral-point-clamped (5L-MNPC) converter is realized by connecting two three-level neutral-point-clamped modules in series. For five-level operation, each dc-bus capacitor voltage of the modular neutral-point-clamped topology should be regulated at one-fourth of the net dc-bus voltage. In this letter, a simple voltage-balancing approach based on the carrier-based modulation scheme is proposed to achieve the above objectives. The proposed approach uses the redundancy switching states along with the current direction and the instantaneous value of the dc-bus capacitor voltage to achieve the voltage balancing in the 5L-MNPC topology. The dynamic performance of the 5L-MNPC topology with the proposed voltage-balancing approach is verified experimentally. [ABSTRACT FROM AUTHOR]

In a modular multilevel converter (MMC), the voltage balance among the submodules is mandatory to generate the multilevel stepped waveform across the load and to ensure the equal voltage stress on the semiconductor devices. In addition, the output power quality (voltage and current waveforms) and the converter reliability greatly depend on the design methodology of a voltage-balancing approach. The improper design of the balancing approach causes higher voltage and current harmonic distortion and device power losses, which further affects the efficiency of the MMC. In this letter, an improved voltage-balancing approach is proposed to reduce the output voltage harmonic distortion and device power losses. The performance of the proposed approach is verified through MATLAB simulations and experimentally on a three-level-flying-capacitor-based MMC system. Also, the performance of the proposed approach is compared with the existing methodology to prove its superiority. [ABSTRACT FROM AUTHOR]

The three-level flying capacitor (3L-FC) submodule significantly reduces the magnitude of circulating currents, voltage ripple, and footprint size and improves the efficiency of the modular multilevel converter (MMC). Due to the above advantages, the 3L-FC submodule becomes an alternative for the conventional half-bridge submodule in the MMC. Each 3L-FC submodule consists of two floating capacitors with different nominal voltage rating. The precharging of floating capacitors without inrush current is one of the major challenges in the 3L-FC-based MMC. This paper proposes a sequence of design steps to precharge the floating capacitors in the 3L-FC-based MMC. The proposed approach is highly effective to charge the outer and inner capacitors of each 3L-FC submodule to their nominal value. The superiority of the proposed approach is verified through the MATLAB simulations and dSPACE/DS1103 experiments on a laboratory prototype of the 3L-FC-based MMC. [ABSTRACT FROM AUTHOR]

In a modular multilevel converter (MMC), the zero-sequence currents at twice the fundamental frequency and its multiples flow through the dc bus and cause dc-bus power fluctuations during unbalanced conditions. These fluctuations appear in dc-bus current, considering that the dc-bus voltage is stiff. In this paper, a model-predictive control is proposed to minimize the ripple in dc-bus current. The proposed approach takes the advantage of internally generated zero-sequence voltage to mitigate the zero-sequence current during unbalanced conditions. To implement the proposed approach, a generalized mathematical model of the MMC, which includes the zero-sequence voltage, is presented. The performance of the proposed approach is verified through MATLAB/Simulink simulations on a 4.16-kV/5-MW system and dSPACE/DS1103-based experiments on a 208-V/3-kW laboratory prototype. [ABSTRACT FROM AUTHOR]

Submodule (SM) capacitor voltage ripple is one of the major concerns in modular multilevel converters (MMCs). Capacitor voltage ripple leads to the double-frequency circulating current (CC) in legs, thereby resulting in a cascading effect of increased peak value of the arm current, semiconductor device stress, and power losses in MMCs. In this study, a model predictive control (MPC) with common-mode voltage (CMV) injection is proposed to minimize capacitor voltage ripple and the magnitude of CC. A discrete-time mathematical model of the MMC with CMV is presented to predict the future behavior of the control variables. The injection of CMV guarantees arm voltage balancing without CC control and long-term stability of MMC without large capacitors. The dynamic and steady-state performances of MPC with CMV injection are verified on an MMC with three-level flying capacitor SMs. A performance comparison between the proposed approach and the conventional MPC is also presented. Simulation and experimental studies show that CMV injection significantly reduces the capacitor voltage ripple and the CC in legs. The proposed approach also improves output voltage and current waveform quality. [ABSTRACT FROM PUBLISHER]

The model predictive control has an ability to achieve multiple control objectives for a modular multilevel converter. This approach has high computational complexity and causes the unwanted switching's leading to a higher ripple in output current and harmonic distortion in output voltage and current waveforms. To solve the issues of computational burden and unwanted switchings, this paper proposes a dual-stage model predictive control approach for a modular multilevel converter. In this approach, the primary objectives are evaluated in first stage corresponding to the redundancy of voltage vectors, while the secondary objectives are evaluated in second stage corresponding to the submodule redundancy. Therefore, the computational burden is significantly minimized without affecting the dynamic response. In addition, a discrete-time model of modular multilevel converter incorporating the common-mode voltage is proposed. The simulation and experimental studies are conducted on a three-phase modular multilevel converter to verify the dynamic and steady-state performance of the proposed approach. The performance comparison between the proposed and conventional model predictive control approach is also presented. [ABSTRACT FROM PUBLISHER]

Arm voltage and submodule (SM) capacitor voltage balancing is a key factor for the safe and reliable operation of modular multilevel converters (MMCs). The arm voltage balancing is achieved through a zero-sequence voltage controller in carrier pulse-width modulation (CPWM). In this study, a dual space-vector pulse-width modulation (SVPWM) technique is proposed for an MMC, which eliminates the external controller for arm voltage balancing. In this approach, the three-phase top and bottom arms are independently controlled using SVPWM. In addition, the capacitor voltage balancing can be achieved using redundant switching vectors. However, this will increase the computational load on the space-vector modulator. Therefore, an external capacitor voltage-balancing approach is proposed to minimize the computational complexity. The proposed approach uses the direction of load current instead of the arm current in SM selection process. As such, the required number of current sensors is reduced to 50% in a three-phase system. The proposed modulation and voltage-balancing approach are simulated and experimentally verified on the MMC system with three-level flying capacitor (3L-FC) SMs. Simulation and experimental results show the successful balancing of the arm voltage and SM capacitors voltage. [ABSTRACT FROM PUBLISHER]

The modular multilevel converter (MMC) has several submodules in cascade. To control the submodule capacitors voltage, a new generalized dynamic voltage balancing algorithm along with a simple pulse width modulator structure is proposed in this paper. With proposed pulse width modulator structure, the dynamic voltage balancing algorithm can be easily implemented with any type of carrier based pulse width modulation (including level-shifted and phase-shifted pulse width modulation) scheme without any modifications. This method does not require the sorting technique for selection of submodule capacitors voltage. The performance of the proposed voltage balancing algorithm is presented for MMC with three-level flying capacitor submodules (MMC-3L-FC). The proposed method is also applicable to the conventional two-level half bridge submodules as well. The effectiveness of the proposed voltage balancing algorithm is verified with the phase-shifted carrier-based pulse with modulation scheme. The results obtained from the MATLAB/SIMULINK simulations on 6-kV/ 2.5-MW system and the dSPACE DS1103-based laboratory prototype of 208-V/3-kVA MMC-3L-FC system are in close relationship, and thus, the proposed methodology is validated. [ABSTRACT FROM AUTHOR]

The high-power voltage source inverters are switched at low frequency to reduce the losses in the inverter. The discontinuous pulsewidth-modulation (PWM) sequences reduce the switching frequency to two-thirds compared to the conventional continuous PWM sequences. At low switching frequency, the output will be rich in harmonics, and synchronization is a must to avoid subharmonics. This paper presents four basic types of synchronized discontinuous PWM (DPWM) sequences that ensure synchronization, three-phase symmetry, and half-wave symmetry. The proposed synchronized DPWM sequences are verified through simulation and experiment on a constant- v/f open-loop induction motor drive. The performance of the proposed DPWM algorithms is studied in the entire modulation region, including the overmodulation region, and is compared with that of the conventional synchronized space vector PWM. A different type of DPWM with low common-mode voltage is suggested for low-modulation region and verified experimentally. [ABSTRACT FROM PUBLISHER]