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In this article, the proposed monolithic gallium nitride (GaN)-based driver uses the diode-emulated technique to reduce reverse conduction through a meta-stable fast (MSF) comparator with sub-0.2-ns deadtime. In addition, an active bootstrap controller with a fast discharge loop is used to reduce parasitic effects to improve the driving capability, thereby increasing the switching frequency. Furthermore, the proposed gate driver with dual $dv/dt$ control can reduce the gate-ringing during turn-on/turn-off. Experimental results show that the GaN-based monolithic driver can achieve an operating frequency of 50 MHz and a slew rate of 120 V/ns. At 50 MHz, the conversion of 48-to-5 V can achieve a peak efficiency of 95.4% at the load current of 3.5 A. [ABSTRACT FROM AUTHOR]

This article presents a one-stage buck converter with an accurate nanosecond ON-time ($T_{\mathrm{\scriptscriptstyle ON}}$) control for 48–1-V direct conversion for automotive applications. In order to overcome the low duty cycle from 48 to 1 V, the proposed high-voltage storage and low-voltage boost (HSLB) bootstrap circuit can reduce the level shifter delay to close to zero and the bootstrap delay to less than 2 ns. In addition, the early comparison $T_{\mathrm{\scriptscriptstyle ON}}$ generator can reduce the comparator delay ($T_{d\_{}{\mathrm{ comp}}}$) to close to zero at steady state to achieve precise nanosecond pulse $T_{\mathrm{\scriptscriptstyle ON}}$. On the other hand, $T_{d\_{}{\mathrm{ comp}}}$ can be quickly extended to increase $T_{\mathrm{\scriptscriptstyle ON}}$ by 540% to achieve fast transient with the recovery time of 3 $\mu \text{s}$ , in case load changes from 200 mA to 1 A. Based on the precise nanosecond $T_{\mathrm{\scriptscriptstyle ON}}$ , the OFF-time is extended by the load-dependent current limiting OFF-time modulation for improving light-load efficiency. Experimental results show that the peak efficiency reaches 96.5%, 95.1%, and 92.8% when $V_{\mathrm {IN}}$ is 12, 24, and 48 V, respectively, for $V_{\mathrm {OUT}} = 1$ V. [ABSTRACT FROM AUTHOR]

This article proposes a single-inductor multi-output converter implemented in $0.153 \mu{\mathrm {m}}$ CMOS process, including the adaptive switchable continuous conduction mode (CCM) and discontinuous conduction mode (DCM) (ASCD) technique, and a five-input crosstalk reduction error amplifier (CREA) to minimize the cross regulation to 0.03 mV/mA and achieve load capability up to 3 W. At ultra-light loads, the proposed ultralow power (ULP) mode is applied to reach 185 nA quiescent current and enhance light load power efficiency. Moreover, the peak efficiency is as high as 94.3% with a chip area of $1.2 \times 1.7$ mm2. [ABSTRACT FROM AUTHOR]

For automobile applications, a high-speed switching 48-to-5 V dc–dc buck converter is implemented in the 0.5- $\mu \text{m}$ CMOS and 0.5- $\mu \text{m}$ gallium nitride (GaN)-on-Si processes. This proposed converter includes a pre-charge tracking technique, a temperature-dependent controlled gate driver, and an adaptive relaxation gate drive control technique. The measurement results of this article show that the efficiency can be increased by about 10.3% and can ensure the driving current capacity of enhance GaN (E-GaN). The built-in local negative feedback loop improves the reliability and reduces $R_{\mathrm{\scriptscriptstyle ON}}$ by 21% to reach the peak efficiency as high as 95.4%. [ABSTRACT FROM AUTHOR]

In this article, a monolithically integrated driver fabricated by 12-V depletion mode gallium nitride (dGaN) and enhanced mode GaN (eGaN) driver is proposed. The proposed driver features an internal temperature-compensated (T-compensated) controller to drive an integrated 650-V eGaN power switch. Due to T-compensated characteristics, a slew-rate enhancement driver can be well-controlled by the fast turn-on (FTO) technique which is supplied by an on-chip regulator with reference voltage circuit. Therefore, the Miller plateau voltage can be tracked correctly by the proposed controller so that the switching frequency can be raised up to 50 MHz and the $\textit {dV}_{\mathrm {DS}}$ / dt slew rate can reach 118.3 V/ns for high efficiency and high switching operation. [ABSTRACT FROM AUTHOR]

This article proposes a dual voltage/current (V/C) inductance controller, which has good impedance tracking capability without any high-voltage stress problems. Besides, the proposed dual-mode phase-locked loop (D-PLL) technique can detect the phase difference between voltage and current of the antenna by fast tracking PLL and the accuracy-improved PLL for inductive and capacitive loads, thereby improving efficiency. Therefore, the 5G small base station on the receiver side (RX) can receive 27.8 W of power with 50% efficiency when the wall thickness to the transmitter side (TX) is 25.2 cm. In the case where the distance between TX and RX is close to zero, 50 W higher power with 90% efficiency can be achieved. Accordingly, the efficiency of resistive and inductive loads can be increased by 13% and 41%, respectively. [ABSTRACT FROM AUTHOR]

Compared to Si FETs, when the main GaN FET is in full zero voltage switching condition, maximum switching loss reduction can be achieved. Therefore, in this article, an active clamp flyback converter with GaN devices that implements fast ZVS by using the proposed dynamic resonant period control (DRPC) technique can reduce large transformer leakage inductance energy loss on the active resonant circuit. As the loading changes, the DRPC technique can dynamically adjust the on-time in auxiliary switch to prevent large voltage stress on the components in the primary side. In full load condition, the leakage energy loss can be reduced, thereby transferring more energy to the secondary side with maximum efficiency up to 94%. [ABSTRACT FROM AUTHOR]

The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μA and reduces the switching power loss through variable switching frequency control. With a load step of 1–20 mA, the transient response time is 1.3 μs and the peak current efficiency is 99.8% at heavy loads. [ABSTRACT FROM AUTHOR]

Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple, and oscillation in single-inductor multiple-output (SIMO) DC–DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in SIMO is proposed for wearable device power solution. Different from the conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. In addition, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. Furthermore, bidirectional dynamic slope compensation conquers subharmonic oscillation and avoids invalid pulses in the energy delivery operation of current-mode SIMO DC–DC converters. The test chip fabricated in the 0.18 μm CMOS process occupies 2.24\, mm^2 active area. Maximum output ripple, overshoot/undershoot, and cross regulation are kept below 40 mV, 27 mV, and 0.0432 mV/mA, respectively. [ABSTRACT FROM AUTHOR]

The predicting correction technique (PCT) is proposed to achieve an adaptive on-time control for ripple-based buck converters. The switching frequency $f_{{\rm SW}}$ variation is suppressed when the PCT technique considers complete parasitic resistances of the components and devices. Even without extra clock-controlled circuits and current sensing circuits, the buck converter operates with a nearly constant $f_{{\rm SW}}$ over a wide load range. Parasitic resistances almost cause no influence and restriction on $f_{{\rm SW}}$. Only input voltage is used to predict the adaptive on-time. Measurement results show only 0.32% in $\Delta f_{{\rm SW}}/f_{{\rm SW}}$ and 5.7 kHz/A in $\Delta f_{{\rm SW}}/\Delta I_{{\rm LOAD}}$ in case of 1.4 A load current change and $f_{{\rm SW}}$ is 2.5 MHz. Consequently, a pseudo-constant $f_{{\rm SW}}$ with well-defined noise spectrum strongly benefits the solution of electromagnetic interference (EMI) for system-on-a-chip (SoC) applications. [ABSTRACT FROM AUTHOR]

In this paper, a class-D audio amplifier which combines the advantages of the phase-shifted carrier pulsewidth modulation (PWM) and the multiple-level carrier PWM is proposed with a dual-level dual-phase carrier (DLDPC) PWM. The proposed closed-loop amplifier includes a second-order integrator and a DLDPC triangular wave generator. Two sets of 180° out-of-phase triangular waves are used as carriers, and each set has its respective offset voltage level with nonoverlapping amplitude. By performing the double Fourier analysis, it can be found that the linearity can be enhanced and the distortion can be reduced with the proposed modulation. Experimental results show that the proposed fully differential DLDPC PWM class-D audio amplifier features a total harmonic distortion lower than 0.01% with an output voltage swing of $\pm$5 V. [ABSTRACT FROM PUBLISHER]

System-on-a-chip (SoC) applications require multiple power supply voltages with the features of low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for the single-inductor quad-output (SIQO) switching converter. This technique manages energy delivery to multiple outputs, facilitates fast transient response, and reduces cross-regulation simultaneously. Moreover, a level bypass detector (LBD) is used to overcome the limitation of significant loading differences among quad outputs in conventional designs because the PSP technique cantransfer additional energy to low-priority outputs to avoid overshoot voltage at high-priority outputs. Furthermore, voltage disturbance can be filtered out using two additional low-dropout regulators that operate as buffers cascaded at two low-priority outputs. Therefore, the SIQO converter that is fabricated in 40 nm CMOS technology satisfies the power requirements in portable electronics given its low cross-regulation of 0.2%, fast transient response of 15 \mu\s, and an output voltage ripple that is smaller than 30 mV. [ABSTRACT FROM AUTHOR]