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Large switching current density and resistance drift remain challenges for phase change memory (PCM) in data storage and neuromorphic computing applications. Here, we address these by electro-thermal and structural confinement in a GeTe/Sb2Te3 superlattice PCM (SL-PCM) with thermally-induced phase change, while observing scalability with bottom electrode diameter. We demonstrate ~ $\text{8-10}\times $ reduction of reset current density $({J}_{\text {reset}})$ and ~ $\text{25-30}\times $ reduction of power $({P}_{\text {reset}})$ in our mushroom cell SL-PCM compared to control Ge2Sb2Te5 (GST) PCM with the same device structure. The SL-PCM devices also exhibit multi-level states with $\sim 10\times $ lower resistance drift compared to control GST PCM. Material characterization and electro-thermal simulations confirm the role of heat confinement in SL-PCM, paving the way towards low-power, high-density memory and data storage. [ABSTRACT FROM AUTHOR]

One of the major roadblocks for filamentary type resistive random access memory is variations in both the write voltage and the read resistance. The variation is inevitable because of the stochastic nature of oxygen ion movement inside the metal oxide. In this letter, we show that by inserting a thin SnO2 layer within the HfO2 switching layer, these variations can be significantly reduced. The TiN/HfO2/SnO2/HfO2/Pt material stack achieves ~ 10 times smaller standard deviation for the high resistance state($>100\text{k}\Omega $) cycle to cycle distribution compared with the control group without the SnO2 layer. The tight high resistance state distribution retained after 107 pulse cycling. Incremental RESET pulse measurement indicates that the thin SnO2 acts as an oxygen stopping layer and thus explains the origin of reduced variability. The concept of an oxygen stopping layer is promising for reducing variability for resistive memory. [ABSTRACT FROM AUTHOR]

Increasing computation demand of machine learning (ML) applications (recommender system, image classification, speech recognition, and so on) calls for the development of specialized hardware for ML and neuromorphic computing. New memories, such as resistive random access memory (RRAM), can be used to store weights of neural networks and to accelerate matrix multiplication, the dominant operation in neural networks. One of the key challenges for RRAM-based neural networks is to achieve bidirectional analog conductance modulation for online training. This article provides a programming scheme (SRA: small RESET voltage amplitude and appropriate SET voltage) to achieve bidirectional analog conductance modulation of RRAM devices. We find that both abrupt and gradual SET can be obtained for the same device. The controlling parameters for modulating the gradual SET behavior are the SET voltage and the local device temperature. We suggest that the filament morphology before SET may be the key to understanding this phenomenon; gradual SET is obtained when the filaments have a single-layer gap in the RESET state, and abrupt SET is obtained when the filaments have a multilayer gap in the RESET state. [ABSTRACT FROM AUTHOR]

High switching current density has been a key bottleneck for phase change memory (PCM) technology. Here, we demonstrate interfacial thermoelectric heating (TEH) as a promising way of tackling this challenge. We use TEH induced by a thin Bi2Te3 interfacial layer to demonstrate $\sim 2\times $ reduction of reset current density (${J} _{\text{reset}}$) and power (${P} _{\text{reset}}$) compared to control PCM devices based on Ge2Sb2Te5 (GST). Measurements of polarity-dependent reset current and power in well-cycled devices reveal the strong TEH caused by the Bi2Te3 interfacial layer. The TEH origin of ${J} _{\text{reset}}$ reduction is further confirmed by electro-thermal simulations. Such TEH-engineered PCM devices are scalable with the bottom electrode diameter and thus could be promising for high density data storage applications. [ABSTRACT FROM AUTHOR]

Using the reduced resistor network developed in Part I of this two-part article, we present practical design guidelines from device to architecture levels to achieve ultrahigh-density 3-D vertical resistive switching memory (VRSM). We first design both hexagon and comb arrays using 7-nm FinFET as pillar driving transistors (pillar drivers). Small-footprint pillar drivers are necessary for a high pillar areal density competitive to 3-D NAND. We then organize the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) to maximize array efficiency and chip density. We investigate the memory and selector requirements, tolerance of parasitic resistances, latency, and energy consumption for both hexagon and comb architectures. The results indicate that the hexagon array with large low-resistance state (LRS) and nonlinearity (NL) is required for ultradense 3-D VRSM. Compared to the comb array, the hexagon array benefits from a continuous WP pattern and yields a better tolerance of parasitic resistances and a smaller latency. The energy consumptions of both architectures are similar. Compared to the most advanced 3-D NAND, 3-D VRSM has higher chip density and shows better potential for future ultradense storage. [ABSTRACT FROM AUTHOR]

Control of cation injection into the switching layer of conductive-bridge random access memory (CBRAM) during switching is a critical factor for CBRAM reliability. Although extrinsic approaches such as the insertion of a transistor in series have proven effective, solutions intrinsic to the CBRAM itself, which are desired for high density cross-point or 3-D vertical memory arrays, are quite limited. In this letter, we show the significant improvement of cycling endurance for Cu-based CBRAM by scaling the switching layer area down to 30 nm in diameter. Further study suggests that the injection of excessive Cu ions into the switching layer is suppressed owing to spatial limitation during the formation of the conductive filament. These results indicate that the area scaling of the switching layer is an effective solution for achieving highly reliable CBRAM devices. [ABSTRACT FROM PUBLISHER]

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array. [ABSTRACT FROM AUTHOR]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

The multilevel capability of metal oxide resistive switching memory was explored for the potential use as a single-element electronic synapse device. \TiN/HfOx/\AlOx/ \Pt resistive switching cells were fabricated. Multilevel resistance states were obtained by varying the programming voltage amplitudes during the pulse cycling. The cell conductance could be continuously increased or decreased from cycle to cycle, and about \10^5 endurance cycles were obtained. Nominal energy consumption per operation is in the subpicojoule range with a maximum measured value of 6 pJ. This low energy consumption is attractive for the large-scale hardware implementation of neuromorphic computing and brain simulation. The property of gradual resistance change by pulse amplitudes was exploited to demonstrate the spike-timing-dependent plasticity learning rule, suggesting that metal oxide memory can potentially be used as an electronic synapse device for the emerging neuromorphic computation system. [ABSTRACT FROM PUBLISHER]

A physics-based compact device model is developed for the conducting-bridge random-access memory (CBRAM). By considering the dependence of ion migration velocity on the electric field, the vertical and lateral growth/dissolution dynamics for the metallic filament are investigated. Both time-dependent transient and “quasi-static” switching characteristics of the CBRAM are captured. Moreover, the I–V characteristics of the CBRAM can be reproduced. By further considering the compliance effect on the size of the metallic filament, the on-state resistance modulation is fitted, and the multilevel capability is included in the model. This model is verified by the experiments data from the \Ag/Ge0.3\Se0.7-based CBRAM cells. This model reveals that experimentally measured switching parameters such as the threshold voltage and the cell resistance are dynamic quantities that depend on the programming duration time. The time-dependent switching process of the CBRAM is quantified, thus paving the way for a compact SPICE model for circuit simulation. [ABSTRACT FROM PUBLISHER]

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (Vth), Vth drift, high resistance state (RESET) resistance (RRESET) drift, and crystallization temperature (Tcrys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. Vth scales down to 0.65–0.5 V (at 25 ^ \circ\C–75 ^\circ\C) for 6-nm-thick \Ge2\Sb2\Te5 (GST), showing that stable read operation is possible in scaled PCM devices. The Vth drift measurement suggests that Vth drift can be attributed to threshold switching field (Eth) drift, whereas Vth0, i.e., Vth at zero thickness, stays almost constant. RRESET drift shows no dependence on the amorphous GST thickness. Tcrys is \sim\!\175 \ ^\circ\C for the device with 6-nm-thick GST, compared with \sim\!\145 \ ^\circ\C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM. [ABSTRACT FROM PUBLISHER]

In this letter, we report ultra-low power (sub-30-nA reset current, I\mathrm {reset}) Ni/HfO2/TiOx/TiN RRAM devices that were fabricated with the rapid thermal oxidation of evaporated titanium. RRAM devices show forming-free, bipolar resistive switching behavior, low-resistive state (LRS) nonlinearity, good data retention, and stability. The resistive switching mechanism is mainly attributed to Schottky barrier modulation induced by \textO^2- migration at the Ni/HfO2 interface. LRS/high-resistive state current conduction is controlled by Schottky emission/trap-controlled space-charge-limited current. The TiOx film is believed to provide a local high-density current for the device, confirmed by conductive atomic force microscope results. [ABSTRACT FROM PUBLISHER]

This letter presents the novel CMOS-compatible all-metal-nitride resistive random access memory (RRAM) devices based on the TiN/AlN/TiN stack. The device has low operation current <100 \mu A, retention of > 3\times 10^{5} s at 150 °C, and ac endurance of up to 10^{5}$ Hz. The device switch characteristics are found to agree with the filamentary switch mechanism. In addition, the RRAM devices built with an additional hafnium nitride capping layer have showed less switch voltage variations and stable switch characteristics. [ABSTRACT FROM PUBLISHER]

In this letter, we examine the role of the Ti capping layer in HfOx-based resistive random access memory (RRAM) devices on the memory performance. It is found that with a thicker Ti capping layer, the fresh device initial leakage current increases and as a result, the forming voltage decreases. In addition, with a thin Ti layer of <3 nm (on top of 8-nm HfOx), there is no resistive switching, while by inserting a thicker Ti layer of 10 nm, the memory window enlarges to about two orders. Very good uniformity has also been observed in thick Ti capping devices, demonstrating the effectiveness in RRAM device engineering. It is believed that the Ti layer serves as an oxygen reservoir, by extracting oxygen during device formation and electrical forming process and facilitates resistive switching thereafter. [ABSTRACT FROM AUTHOR]

A SPICE compact model is developed for metal-oxide-based resistive random access memory (RRAM). The model includes the critical impact of temperature change and temporal variation. Using experimental data from \HfOx-based RRAM, the model reproduces both the voltage–time relationship and the cycle-to-cycle variation in the RESET of the memory cells. [ABSTRACT FROM AUTHOR]

The reset mechanism of metal oxide RRAM has been attributed to oxygen ion migration assisted by Joule heating. Here, we present a phenomenological model to provide a unified explanation for both the unipolar and bipolar resistive switching mechanisms. Numerical simulation results reveal that the switching mode is determined by the electrode/oxide interface property. Without/with an interfacial barrier, unipolar/bipolar switching behavior is obtained. This model combines the previous thermal dissolution model and ion migration model and thus can explain many experimental observations such as the electrode-material-dependent switching polarity and the voltage–time dilemma between fast switching and long retention. [ABSTRACT FROM AUTHOR]

\Al2\O3-based RRAM devices were fabricated using atomic layer deposition under 100 ^\circ\C and 300 ^\circ\C deposition temperatures, respectively, and their resistance-switching behaviors were investigated. Both devices show unipolar switching if the top electrode (TE) is made of Ti/Al, whereas the bipolar phenomenon is observed when TE is pure aluminum. Devices fabricated at higher temperature give better uniformity and higher resistance ratio. Ultralow RESET current (\sim\!\!\1\ \mu\A) was obtained, together with adequate voltage margin. [ABSTRACT FROM AUTHOR]