Search

The carrier-based pulse width modulation (CBPWM) with zero-sequence component injection is equivalent to the space-vector PWM (SVPWM), and hence it can be taken as a simplified alternative to the SVPWM. However, it is quite complex to calculate the zero-sequence component in CBPWM for three-level (3L) converters such as the T-type converter, making the 3L SVPWM still have a large computation burden. In this letter, unified expressions for the zero-sequence component are analytically derived, and the modulation waves of 3L SVPWM can be directly calculated by only 7 simple equations with 3 steps. The computation burden for implementing 3L SVPWM is therefore significantly reduced without sector determination, calculation and assignment of dwell times. [ABSTRACT FROM AUTHOR]

Given the high complexity of the conventional three-level space-vector pulsewidth modulation (3L SVPWM), simplified SVPWM algorithms are usually adopted instead. However, existing simplifications for 3L SVPWM still have a large computation burden, which limits its applications, e.g., in high-switching-frequency silicon-carbide converters with a short computation period. In this letter, based on a typical simplified algorithm known as the center-aligned 3L SVPWM, a simplified analytical algorithm in abc coordinate is proposed. The reference-voltage-vector adjustment and the calculation of modulation waves are unified based on the center-aligned SVPWM. The modulation waves can be analytically derived by only eight simple equations, without sector determination, calculation, and assignment of dwell times. Consequently, the complexity of implementing the 3L SVPWM is significantly reduced. [ABSTRACT FROM AUTHOR]

In a three-phase three-level grid-connected inverter, the ac output current ripple actually fluctuates four times per switching period with each fluctuation generating some core loss. However, only the two larger fluctuations are considered in most loss estimation methods, resulting in a smaller core loss evaluation. In this letter, an alternative method has, hence, been proposed, beginning with the deduction of fundamental and ripple equivalent circuits from the inverter. These circuits permit current ripple to be calculated, from which its four fluctuations are all considered for forming the dual current-ripple envelopes (DCREs). These DCREs, together with the fundamental current and a selected core loss model, can then be solved to give the estimated fundamental and ripple core loss values. The nonlinear characteristic of the filter inductor has also been considered in the calculation of the DCREs and the core loss. The estimated values have eventually been verified through testing with a 10-kW three-phase T-type three-level grid-connected inverter. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]

The adoption of silicon carbide (SiC) MOSFETs and SiC Schottky diodes in power converters promises a further improvement of the attainable power density and system efficiency, while it is restricted by several issues caused by the ultrafast switching, such as phase-leg shoot-through (“crosstalk” effect), high turn-on losses, electromagnetic interference (EMI), etc. This paper presents a split output converter, which can overcome the limitations of the standard two-level voltage source converters when employing the fast-switching SiC devices. A mathematical model of the split output converter has been proposed to reveal how the split inductors can mitigate the crosstalk effect caused by the high switching speed. The improved switching performance (e.g., lower turn-on losses) and EMI benefit have been demonstrated experimentally. The current freewheeling problem, the current pulses and voltage spikes of the split inductors, and the disappeared synchronous rectification are explained in detail both experimentally and analytically. The results show that the split output converter can have lower power device losses compared with the standard two-level converter at high switching frequencies. However, the extra losses in the split inductors may impair the efficiency of the split output converter, which is verified by experiments in the continuous operating mode. A 95.91% efficiency has been achieved by the split output converter at the switching frequency of 100 kHz with suppressed crosstalk, lower turn-on losses, and reduced EMI. [ABSTRACT FROM AUTHOR]

Presents corrections to author information in the above named paper. [ABSTRACT FROM AUTHOR]