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For very high frequency (VHF) class Φ2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this article, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. First, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. In addition, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12 MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency. [ABSTRACT FROM AUTHOR]

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion. [ABSTRACT FROM AUTHOR]

In the quest for novel, scalable and energy-efficient computing technologies, spin-based logic devices are being extensively explored due to their potential for nonvolatility, small cell area, and low operational power. Spin torque majority gate (STMG) is one of the most promising options for beyond CMOS nonvolatile logic circuits for normally-off computing. However, significant problems arose with cascade-ability, signal nonreciprocity, and complicated circuit configurations based on STMG. In this paper, a novel magnetic majority gate (MMG) logic has been proposed, utilizing both spin transfer torque and spin–orbit torque effects. A logic family including and/nand and or/nor functions can be achieved with an easy configuration and under a stable operation. Communication between logic units is realized by spin current injection through a nonferromagnetic metal wire to ensure its cascade-ability and nonreciprocity to design multiple logic-depth circuits. With all of these advantages, the proposed cascadable MMGs can be utilized to design logic functions such as the BUFFER/ NOT, XOR/ XNOR, and complicated logic gates, which pave the pathway for designing robust and comprehensive logic circuits using full spintronic devices. [ABSTRACT FROM AUTHOR]

Exploring high-performance controller for buck converter is challenging since it can be easily affected by converter model accuracy. In this paper, a novel nonaveraged current discrete-time (NCD) model is proposed, in which inductor current is expressed as time-varying equations during switch-on and switch-off states. It achieves higher accuracy than the conventional averaged model at high-frequency range, thus can be used to optimize high-speed controller design. Based on the NCD model, a multiloop minimum switching cycle (MMSC) control strategy, composed of output feedback (OF), line feed forward (LFF), and reference feed forward (RFF) loops, is proposed and tuned for buck converter operating in continuous conduction mode. Mutual influences among three loops are considered and eliminated by specifically designed LFF and RFF compensations, which adapt the OF compensation. With consideration of sampling and calculation delays, relationship between transient switching cycles and geometric center of controller poles is discovered from a calculated output voltage error series. Furthermore, theoretical minimum switching cycles are calculated by moving the center inside the unit cycle of complex plane, which ensures system stability. Moreover, load/line transient response and reference tracking time are simultaneously optimized to the minimum switching cycles. Effectiveness of the controller is proved by converter closed-loop pole/zero plots, transient response simulations, and experiments. [ABSTRACT FROM AUTHOR]

For discontinuous conduction mode (DCM) dc–dc converters with digital sensorless current mode (DSCM) control, an observed current error occurs, owing to a low-accuracy current observer. Moreover, a reference current error occurs due to a low-accuracy current controller or a finite dc gain of current loop. Conventionally, the observed current is compensated to increase current regulation accuracy, whereas the reference current error is neglected. However, for charge balance principle (CBP)-based DSCM (CBP-DSCM) control, this paper proves that the reference current should be compensated in a same quantity to that of observed current. Otherwise, single or unequal compensation leads to output voltage steady-state error. For this reason, a dual current error compensation strategy for CBP-DSCM control is proposed. It compensates the errors in a same quantity through a current error observer, which considers parasitics and calculates the current errors without approximation. To verify the proposed strategy, small-signal models with parasitics for both the converter and the controller are constructed by differential functions of key variables. Furthermore, converter stability is analyzed at typical operation condition, while the stability at various operation conditions is verified through robustness analysis. Finally, simulations and experimental results verify the analysis and the improved transient response of the converter. [ABSTRACT FROM AUTHOR]

For a sensorless predictive current controlled boost dc–dc converter, its small-signal model that contains a number of parasitic parameters, is derived in this paper. This model indicates that the type of system becomes type 0 even with the correction of voltage loop proportional–integral controller, leading to the existence of output voltage steady-state error. Then a self-correction differential current observer (SDCO) is proposed to eliminate this steady-state error and gain high transient response speed. The self-correction part of the SDCO makes the system become type 1 to achieve no steady-state error for output voltage, whereas the differential part can guarantee that the intermediate calculation results do not overflow. By carrying out a series of simulation verifications, further investigation proves that the proposed algorithm has good robustness. Finally, the effectiveness of the proposed algorithm is verified by experimental results. [ABSTRACT FROM PUBLISHER]

For a sensorless predictive-peak-current-controlled boost converter, the output voltage steady-state error cannot be eliminated by voltage loop PI controller. The basic cause for this is investigated through analysis and theoretical approaches. To eliminate the voltage steady-state error and achieve high-accuracy current estimation, a comprehensive compensation strategy is proposed. First, a compensation algorithm for output voltage sampling is introduced. It can not only effectively eliminate the output voltage steady-state error but also guarantee current observer convergence. The compensation schemes for component parasitic parameter effects and switching delay are also investigated. With this comprehensive compensation strategy, both the system transient response and current estimation accuracy are greatly improved. Finally, the effectiveness of the proposed algorithm is verified by experimental results. [ABSTRACT FROM AUTHOR]

An enhanced electrostatic discharge (ESD) power clamp for an antenna switch controller with silicon‐on‐insulator (SOI) complementary metal‐oxide‐semiconductor (CMOS) technology is presented. The gate drive voltages of larger n‐type metal‐oxide‐semiconductor transistors in a stacked configuration of a RC‐triggered power clamp have been optimised to obtain larger discharging capability and shorter turn‐on time compared to the conventional topology. The proposed ESD power clamp circuits are implemented in a double‐pole five‐throw antenna switch controller and the experimental results confirm the validity of this approach. [ABSTRACT FROM AUTHOR]