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Transfer-molding process is enjoying growing interest when aiming for novel high-power density system-in-packages (power SiPs), where not only transistors and diodes but also drivers, passives, coils, and transformers are supposed to be integrated in one package. Encapsulating modules in a transfermolding process induces higher mechanical load onto module components compared with conventional silicone potting. Previous investigations have shown that integration of delicate components as ferrite cores into molded packages is not as trivial as integration of conventional surface-mount devices or power semiconductors; the brittle ferrites tend to fracture during the encapsulation process, resulting in higher ferrite core loss. The current study aims to identify main root causes for ferrite core cracking during manufacturing of molded power SiPs. The test vehicle is a symmetrical printed circuit board-based package with three pairs of E-shaped ferrite cores. The epoxy molding compound deployed here is characterized to enable filling simulations. Because technical datasheets of ferrites typically lack specifications of mechanical properties, ferrite materials are analyzed in more detail. Filling simulations and thermomechanical simulations are performed to gain insight into process-induced stress, which may induce cracks in the ferrites. In addition, different ferrite designs are evaluated regarding core losses and mechanical stability and, thus, their tendency to fracture. [ABSTRACT FROM AUTHOR]

In this paper, bond via array (BVA) wirebond is used to achieve compact vertical integration and improve the electrical performance for system in package (SiP). Two techniques are presented. In the first technique, BVA wirebonds are utilized to integrate some passive or active components vertically onto other components. This significantly reduces the horizontal footprint of the entire SiP. In terms of electrical performance, this vertical integration provides much lower parasitic inductance than conventional 2-D horizontal integration design because of shorter interconnection. For example, the proposed technology can significantly reduce power delivery network impedance compared to a conventional design. In the second technique, we propose BVA wirebond wires as an electromagnetic interference (EMI) shield between different domains within SiP. This provides a lower cost solution for EMI shielding, particularly when regions within a package need to be shielded. [ABSTRACT FROM PUBLISHER]

In this paper, a power/ground (P/G) pin assignment method using simulated annealing (SA) for large-scale high-pin-count ball-grid-array (BGA) packages is proposed. Two objective functions describing the power integrity (PI) and signal integrity (SI) of the pinout are introduced. The SA algorithm is customized to meet the needs of the pin assignment problem. Accelerating strategies are introduced, and some special considerations for customized SA optimization are discussed. The SA method can generate large-scale P/G pinout with any power–ground–signal pin ratios ( P\mathrm {0}/G\mathrm {0}/S\mathrm {0} ) in a few minutes. Large-scale BGA packages with more than 2000 pin numbers including the I/O, core, and different-pair blocks can be generated by the proposed SA method quickly, with a similar PI and SI performance compared to the products from Xilinx and Altera. [ABSTRACT FROM PUBLISHER]

This work proposes a method based on microstrip multi-size T-resonators to increase the accuracy of extracted dielectric characteristics. The dielectric characteristics of an ultra-thin and low-loss build-up substrate for system-in-package modules are obtained, which closely correspond to the measured S-parameters. An electromagnetic simulation is performed to verify the extracted dielectric characteristics. The proposed method is also used to improve the accuracy of prediction of far-field radiated emission at resonant frequencies from a microstrip component. [ABSTRACT FROM PUBLISHER]

In this paper, we present a complete 700-2,600 MHz RF SiP module for micro base station. This RF SiP design integrates transmitter, receiver, feedback module, ADC/DAC and CLK module. The module consists of two multi-layer organic substrates that are vertically stacked using BGA interconnections. With the integration of 33 chips and about 600 passive components, this RF SiP module retains small form factor and measures 5.25 cm × 5.25 cm × 0.7 cm. The RF input signal transmission path insertion loss is less than 0.34 dB and the return loss is less than −14 dB at 2.6 GHz. Full load thermal simulation result indicates that each chip junction temperature is below 100 °C. We summarize the RF SiP module design, assembly and simulated thermal characteristics. The proposed RF SiP can generally be characterized by small size, low cost and short development cycle. [ABSTRACT FROM AUTHOR]

Both commercial and noncommercial systems must manage their system effectiveness through the acquisition and operational stages of their life cycles. Once the system design baseline is defined and instantiated, then the challenge is to affordably sustain the physical system elements (SEs), which evolve in response to changing external influences. These influences may include frequent asynchronous SE obsolescence (hardware and software), increased functional requirements, or even external system regulatory changes (i.e., security, import and export laws, and safety standards). This paper specifically addresses the influence of SE obsolescence within a system life cycle. It proposes a model to optimize for the affordability of changes through a defined system life cycle by forecasting SE revisions. Firstly, each system element is described by a unique SE life cycle curve, and secondly, this curve forecasts the possible obsolescence revision sequences through a selected system life cycle. Models are proposed for the system element life cycle curve and the obsolescence revision sequencing. These models are particularly useful in situations where the SEs are independent of one another within a defined system context. In this way, optimized SE changes can be deployed to maximize the operational effectiveness of the system through its life cycle. [ABSTRACT FROM PUBLISHER]

This paper presents the visualization of the fluid/structure interaction (FSI) in molded integrated-circuit (IC) packaging. The complexity and high cost of the experimental setup in the molded packaging make the FSI visualization difficult during the encapsulation process, particularly for tiny and thinned chips in IC packages. To address this problem, we fabricated a scaled-up transparent molded package, and the encapsulation process was experimentally performed to visualize the FSI phenomenon. Two scaled-up (single- and stacked-chip) IC packages were considered in the experiment to investigate the FSI, flow front advancement, and void formation. The void formation mechanisms for both imitated IC packages were also studied. Moreover, finite-volume and finite-element codes, via the mesh-based parallel code coupling interface method, were used to describe the physics of FSI during the encapsulation. The predicted flow front advancement, flow profiles, and chip deformation were validated with the experimental results. Hence, this paper is expected to provide a better understanding of the FSI phenomenon during the IC encapsulation. [ABSTRACT FROM AUTHOR]

Flexible printed circuit board (FPCB) can be an alternative to the rigid printed circuit board (PCB) because of its excellent flexibility, twistability, reduced thickness, and light weight. In a flow environment, although the deflection and stress induced are often ignored by PCBs, these are key factors that affect the reliability of FPCBs. Thus, this paper aims to examine the effect of flow velocity, component thickness, types of component arrangement, misalignment, and inclination on a typical FPCB electronics under flow condition. These factors are found to significantly affect the deflection and stress levels of FPCBs. On the basis of the results, a few design strategies are suggested to FPCB designers to develop more reliable products. In this paper, a fluid-structure interaction (FSI) study was performed using the fluid solver FLUENT and the structural solver ABAQUS, coupled online by the mesh-based parallel code coupling interface. A simple experiment was also performed to validate the FSI numerical technique used. The research findings in this paper are believed to be valuable and important to the FPCB industries. [ABSTRACT FROM PUBLISHER]

Electronic circuit boards of computers consist of components which generate substantial amounts of heat during their operation. Among these, the microprocessor chip is one of the major sources of heat generation. In high-performance processor chips, the rates of heat generation are also correspondingly high. The performance of the chips themselves, as well as that of the neighboring electronic components are affected by the temperature levels attained, which in turn depend on the heat dissipation capability. Effective thermal management of microprocessor chips, following precise thermal characterization, is essential to avoid their untimely failure due to overheating. The selection of an appropriate cooling methodology and the design of an efficient cooling system for the microprocessor chip essentially require a clear knowledge of the heat dissipation rates during its operation. A comprehensive database of heat dissipation from microprocessor chips as a function of the activity level, based on actual measurements, is rare to find in the literature. A major reason for this is that conventional intrusive measurements on and around the chip are quite insufficient, as they will alter the performance, while the system is under operation. To overcome this, a nonintrusive digital interferometric measurement has been devised in this paper for obtaining the in situ temperature distributions and the heat dissipation patterns around the microprocessor chip, while it is under operation. The interferometric method utilizes interference of coherent laser beams to make measurements in the thermal field around the heat-dissipating component. An Intel Pentium 4 microprocessor with its integrated heat sink was used for experimentation. The computational load on the processor was varied utilizing a software package, thus varying the heat generation rates, and the base temperature of the fins in the heat sink attached to the microprocessor. Interferometric measurements were made to obtain the temperature distribution in the medium, and the patterns of heat dissipation from the fins' surfaces. Indicators of the heat transfer behavior, namely, the local heat flux values and the heat transfer coefficients were obtained from the experiments, using digital image processing techniques. Experiments were conducted at various fin-base temperatures, under free and forced convection conditions, to characterize the effect through a database of the heat dissipation level. In essence, a nonintrusive temperature measurement method coupled with digital image processing techniques has been successfully used for convective heat transfer studies on the microchip while the microchip is under operation. [ABSTRACT FROM PUBLISHER]

The purpose of this paper is to address the de-embedding issue of millimeter-wave (mmWave) and sub-mmWave measurements and circuit design by extensively comparing several commonly used methods and by proposing a new full-matrix calculation-based de-embedding methodology. The comparison aims to investigate the impacts of different de-embedding methods on mmWave and sub-mmWave circuit design. A new de-embedding method has been proposed to achieve more accurate results on mmWave and sub-mmWave range. In this method, all possible extrinsic elements are subtracted from the measured device under test data by matrix calculation to eliminate the error from equivalent circuit. The influence of parasitic elements on the fT and fMAX are investigated. The comparison of the different de-embedding methods for transistors are performed up to 170 GHz, the results showed that the proposed method has good accuracy even at very high-frequency and it is suitable for mmWave and sub-mmWave measurements and circuit design. [ABSTRACT FROM PUBLISHER]

This paper presents an approach for the extraction of passive macromodels of large-scale interconnects from their frequency-domain scattering responses. Here, large scale is intended both in terms of number of electrical ports and required dynamic model order. For such structures, standard approaches based on rational approximation via vector fitting and passivity enforcement via model perturbation may fail because of excessive computational requirements, both in terms of memory size and runtime. Our approach addresses this complexity by first reducing the redundancy in the raw scattering responses through a projection and approximation process based on a truncated singular value decomposition. Then we formulate a compressed rational fitting and passivity enforcement framework which is able to obtain speedup factors up to 2 and 3 orders of magnitude with respect to standard approaches, with full control over the approximation errors. Numerical results on a large set of benchmark cases demonstrate the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

Interconnects in radio frequency (RF) packages have a strong tendency to deteriorate RF performance, especially in high-frequency systems. In this paper, comparison is made between the wirebonded and embedded flip-chip packages. X-band silicon-germanium low-noise amplifiers are used to evaluate the performance of these interconnects. Measured results show that the embedded flip-chip packages have better RF performance than the wirebonded packages for X-band applications. At 9.5 GHz, the flip-chip interconnects contribute only 0.4 dB of insertion loss, while the wirebond interconnects contribute 2.2 dB of insertion loss. The flip-chip and wirebond interconnects are modeled and validated against measured results from 8 to 20 GHz. For the first time, multiple dies are put together in a single liquid crystal polymer package to compare the packaging effects, and to demonstrate the feasibility of embedding multiple dies within a single package for highly integrated solutions. [ABSTRACT FROM PUBLISHER]

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored. [ABSTRACT FROM PUBLISHER]

With the increase of driving current and power density, the thermal fatigue characteristics of die attach materials have become an important issue impacting the long-term reliability of high-brightness light-emitting diodes (HB LEDs). In this paper, an accelerated power cycling method is used to predict the thermal fatigue life of die attach materials for packaged HB LEDs. The thermal fatigue life of Au80Sn20 eutectic and silver paste is investigated at driving currents of 650, 675, and 700 mA. Changes in the thermal resistance of die attach materials are monitored by the noninvasive structure function method based on the measurement of transient temperature response curves through power cycling experiments. Results of C-mode scanning acoustic microscopy and cross-sectional scanning electron microscopy indicate that delamination is the main failure mechanism of the die attach materials under thermal fatigue stress. Furthermore, the thermal fatigue life of die attach materials can be derived from the relationship between lifetime and temperature difference according to the Coffin-Manson relationship. The results suggest that Au80Sn20 eutectic possesses a longer thermal fatigue life than silver paste at the same temperature difference of thermal fatigue stress. [ABSTRACT FROM AUTHOR]

Application of electronic devices on automotive vehicles keeps increasing, and adoption of ball grid array (BGA) package is inevitable in the industry. Vibration loading to a vehicle provides another hazardous stress to the BGA assembly in addition to thermal one. In this paper, random vibration test on a daisy-chained BGA assembly is conducted with a real-time monitoring of resistance. BGA assemblies with leaded and lead-free solders are tested at once in the test. The changes of resistance before the occurrence of failure are investigated and a precursory resistance pattern before the failure of BGA assemblies is identified at the both solder types. Analyses on the failure locations confirm the localized failures on the BGA ball matrix. To investigate the generating mechanism of the precursory resistance pattern in the BGA assemblies, a numerical model of the mechanism is suggested and experimentally demonstrated. Based on the studies, a noble design of BGA assembly is suggested for the implementation of prognostics and health monitoring in vibration environment. [ABSTRACT FROM PUBLISHER]

The epoxy mold compound (EMC) used in encapsulated microelectronic devices affects the thermal, electrical and mechanical performance of the devices. Although many studies have been conducted to test the reliability, thermal and mechanical aspects of the problem not much literature can be found analyzing the impact of the mold compound on the electrical performance of the devices. In this paper we present the results of carefully designed experiments that evaluate the effects of the EMC in the electrical performance of high-power high-frequency laterally diffused metal oxide silicon transistors. [ABSTRACT FROM PUBLISHER]

A direct and deleterious effect on packaging reliability has been observed during elevated temperature isothermal aging for fine-pitch ball grid array (BGA) packages with Sn-1.0Ag-0.5Cu (SAC105), Sn-3.0Ag-0.5Cu (SAC305), and Sn-37Pb solder ball interconnects. Package sizes ranging from 19 mm with 0.8-mm-pitch BGAs to 5 mm with 0.4-mm-pitch μ BGAs with three different board finishes (ImSn, ImAg, and SnPb) were evaluated. The aging temperatures were 25°C, 55°C, 85°C, and 125°C, applied for a period of 6 mo. Subsequently, the specimens were thermally cycled from -40°C to 125°C with 15-min dwell times at the high temperature. Weibull analysis of failures versus cycle number show a ~ 50% reduction in package lifetimes when aged at 125°C compared to the same at room temperature, with less dramatic but measurable reductions in lifetime at 85°C and even 55°C. In contrast, the reliability performance of Sn-37Pb is much more stable over time and temperature. The degradation was observed for both SAC alloys on all tested package sizes and board finishes. For the 19-mm SAC105 case, for example, there was a 53% (32%) reduction of characteristic lifetime at 125°C (85°C) compared to room temperature aging. The trends were in the expected directions; namely, the reliability was reduced when using higher aging temperatures, smaller solder balls, and SAC105. The dominant failure mode can be associated with the growth of Cu6Sn5 intermetallic compounds during the aging, particularly on the pad side. [ABSTRACT FROM AUTHOR]

In recent years, there has been growing demand to increase the power density in power modules. Therefore, the thermal management of power modules has become more and more critical. In this paper, we show that conventional single-sided power module with wire-bond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. The plate-bonded power module has been proposed to resolve this issue. However, the thick copper plate embedded in the power module induces large thermomechanical stress during temperature cycling, leading to poor reliability. To reduce the thermomechanical stress without significantly compromising the thermal performance, a trenched copper plate power module is designed and presented. A parametric study shows that the maximum von Mises stress and plastic strain in the solder layer can be reduced by 18.7%, and 67.8%, respectively, if the single piece of copper plate is replaced by a 3 × 3 trenched copper plate. [ABSTRACT FROM PUBLISHER]

In thermosonic wire bonding, a free air ball (FAB) created by electronic flame-off (EFO) is crucial to a reliable first bond. To reveal the mechanisms of FAB and ripple formation, the dynamic FAB formation process was monitored and analyzed with a high-speed camera and digital data acquisition system. FAB formation was found to occur in four stages: initiation, preheating, melting, and solidification. The FAB formation speed and model depend only on the EFO current. The FAB formation speed can be as high as 90.4 μm/ms at an EFO current of 60 mA. A minimum EFO time is required for FAB formation, which depends on the EFO current. A semiempirical model FAB=ηln[I(t - 0.5 tmin)]- c, was developed to describe the relationship between the FAB size and the EFO time at different EFO currents. The ripple formation mechanism was investigated by analyzing the solidification stage images. Transient droplet vibration caused by high-speed rolling-up and skin-forming solidification in the molten gold drop caused by a large temperature gradient are two major factors in ripple formation. This analysis is expected to be useful for understanding the FAB formation mechanism and optimizing the EFO parameters. [ABSTRACT FROM PUBLISHER]

The framework for this paper is the growing concern about the worldwide increasing energy consumption of telecommunications systems and data centers, and particularly the contribution of the thermal management system. The present energy usage of these systems is discussed, as well as the relationship between cooling system design and the total cost of ownership. This paper identifies immediate and future thermal bottlenecks facing the industry, ranging from technological issues at the component and system level to more general needs involving reliability, modularity, and multidisciplinary design. Based on this enumeration, the main challenges to implementing cooling solutions are reviewed. Particular attention is paid to implementing liquid cooling, since this technology seems the most promising to addressing the key thermal bottlenecks, and improving the future sustainability of thermal management in the telecom and data center industry. Finally, an outlook is presented toward future potential challenges. [ABSTRACT FROM PUBLISHER]

This paper deals with 24-GHz circuits developed by exploiting a system-in-package approach. In order to reduce the cost as much as possible, a standard multilayer printed circuit board (PCB) technology has been adopted. Such a circuit consists of a package built utilizing a 0.3-mm thick fiber-glass substrate with 3.38 relative permittivity. The contacts between the substrate and the mother board are realized along the package perimeter exploiting 0.6-mm via-hole metalization and half halo shield soldering pad. First, the developed package is simulated and optimized by means of commercial electromagnetic software. Then a prototype is fabricated and measured. The obtained results show that the whole frequency band from DC to 30 GHz can be covered. A packaged 26.5-mm straight microstrip line exhibits an |S11| value better than -12 dB and an |S21| value of about -1.4 dB at 24 GHz. This value is only 0.6-dB worse than that of the unpackaged line. A single-balanced diode mixer and a low-noise amplifier (LNA) for industrial, scientific, and medical applications are then designed. The integration of these building blocks within the PCB package is finally demonstrated and experimentally verified. The packaged mixer shows a 6.8-dB conversion loss. The packaged LNA, instead, features a 9.1-dB gain with a 3.4-dB noise figure. [ABSTRACT FROM PUBLISHER]

We investigate high-quality (high-Q) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded wafer-level ball grid array (eWLB) package. The eWLB is an innovative package technology introduced recently for wireless applications. The technology has outstanding capabilities especially for high-frequency and millimeter-wave package design. We demonstrate that inductors realized in the eWLB fan-out area have negligible substrate losses and lower parasitic capacitances compared to inductors in the eWLB fan-in area. As a result, the inductors implemented in the fan-out area offer significantly higher quality factors and higher self-resonance frequencies. We investigate the effects of the chip-to-package interconnection. We show that the chip-to-package transition creates a bottleneck for the integration of high-Q inductors. We demonstrate the advantages of inductors in the fan-out area of the eWLB on the example of a 6-GHz voltage-controlled oscillator (VCO) chip manufactured in a 65-nm complementary metal-oxide-semiconductor process and assembled in an eWLB package. For the LC tank of this example, we use a 1.1-nH high-Q differential fan-out eWLB inductor to reduce the phase noise. For comparison, we investigate a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package. Our measurement results demonstrate lower phase noise and higher output power for all VCOs with inductors embedded in the RDL compared to the reference VCO with the on-chip inductor. The measured phase noise for the VCO with the eWLB inductor in the fan-out area is in the best case 9 dB lower than that of the reference VCO with the on-chip inductor. The presented results prove the integration concept and demonstrate the excellent potential of embedded inductors realized in the fan-out area of the eWLB package. [ABSTRACT FROM PUBLISHER]

This paper focused on the feasibility of preparing Sn-Ag-In ternary solder bumps with small size by two-step electroplating. The interfacial reaction and shear strength between three different solders (Sn2.2Ag, Sn1.8Ag9.4In, and Sn1.6Ag21.7In) and Cu under bump metallization (UBM) were investigated. After the reflow for 10 min, η Cu6(Sn,In)5 and ε Cu3(Sn,In) intermetallic compounds (IMC) were formed at the interface near the solder matrix and Cu UBM, respectively. Indium addition lowered the reflow temperature and improved the interface between solder and IMCs. The mean shear strength of Sn1.8Ag9.4In solder bump was higher than that of Sn2.2Ag and Sn1.6Ag21.7In solder bumps. After long time reflow, the mean shear strength increased. [ABSTRACT FROM PUBLISHER]