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The number of speedpaths in modern high-performance designs is in the range of millions and, due to unmodelled electrical effects, they are difficult to be measured accurately before the first silicon samples are available. As a consequence, clock tuning elements are employed to aid the post-silicon clock tuning. However, as the number of these elements continues to grow, it becomes increasingly difficult to determine their configurations in a compute effective manner. In this paper we describe a novel exact algorithm for post-silicon clock tuning, which employs smart pruning techniques that exploit the characteristics of the clock tuning buffers. [ABSTRACT FROM AUTHOR]

Lifetime performance of digital integrated circuits degrades as a consequence of circuit aging. In the past few years, there has been extensive research to reduce the impact of aging by different design techniques, or to predict the degradation and adapt the circuit accordingly. In this paper, we explore a novel perspective to this problem by exploiting the presence of clock tuning elements in high-performance designs. By combining on-chip sensors to predict setup or hold-time violations with the clock tuning elements, we provide an effective self-tuning mechanism for each circuit sample. The proposed method can operate in-system to prolong the circuit's maximum performance in its unique operating environment. [ABSTRACT FROM AUTHOR]

Motivated by the increasing design for test (DFT) area overhead and potential performance degradation caused by wrapping all the embedded cores for modular system-on-a-chip (SOC) testing, this paper proposes a solution for reducing the number of wrapper boundary register (WBR) cells. By utilizing the functional interconnect topology and the WBRs of the surrounding cores to transfer test stimuli and responses, the WBRS of some cores can be removed without affecting the testability of the SOC. We denote the cores without WBRs as lightewrapped cores and present a new modular SOC test architecture for concurrently testing both the wrapped and the light-wrapped logic cores. Since the WBRs of cores that transfer test stimuli and test responses for light-wrapped cores become shared resources during test, conflicts arise during test scheduling that will negatively impact the test application time. As a consequence, to alleviate this problem, we present a novel test access mechanism (TAM) design algorithm for the proposed SOC test architecture. We conduct experiments on several SOC benchmark circuits and demonstrate that, with an acceptable increase in test application time, the number of WBRS can be significantly decreased. This will ultimately lessen the necessary DFT area for modular SOC testing and reduce the propagation delays between cores. [ABSTRACT FROM AUTHOR]

This paper addresses the testability problems raised by intellectual property cores with multiple clock domains. The proposed solution is based on a novel core wrapper architecture and a new wrapper design algorithm. It is shown how multifrequency at-speed test response capture can be achieved via the design of capture windows without any structural modifications to the logic within the embedded core. The new features in the core wrapper architecture, which introduce limited hardware over- head, can also synchronize the external tester channels with the core's internal scan chains in the shift mode. Thus, the wrapper implementation space can be explored in order to efficiently utilize the available tester bandwidth while meeting the constraints on the maximum internal shift frequency that guarantees low testing time within the given power ratings. Using experimental data, the benefits of the proposed solution are demonstrated by analyzing the tradeoffs between the number of tester channels, testing time, area overhead, and power dissipation. [ABSTRACT FROM AUTHOR]

This paper analyzes the test memory requirements for corebased systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chain designs. Although useless test data does not represent any relevant test information, it is often unavoidable, and leads to the tradeoff between the test bus width and the volume of test data in muitiple scan chain-based cores. Ultimately, this tradeoff influences the test access mechanism design algorithms leading to solutions that have either short test time or low volume of test data. Therefore, in this paper, a novel test methodology is proposed which, by dividing the wrapper scan chains (WSCs) into two or more partitions, and by exploiting automated test equipment memory management features, reduces the amount of useless test data. Extensive experimental results using ISCAS'89 and ITC'02 benchmark circuits are provided to analyze the implications of the number of WSCs in the partition, and the number of partitions on the proposed methodology. [ABSTRACT FROM AUTHOR]

Discusses the possibility to control rising costs of chip test by putting more test resources on-chip. Factors to consider in moving test resources onto the system-on-chip; Cost projection made in the International Technology Roadmap for Semiconductors; Analysis of the performance of several test data compression environments that can exploit test-set regularities.