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We report measurements of multiple hot-carrier (HC) stress and high-temperature anneal cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS technology. We model this cycled HC degradation anneal assuming Si–H bond breakage during stress and bond passivation during anneal, with the bond dissociation and passivation energies following a bivariate Gaussian distribution. Our model can describe multiple stress and anneal time scenarios well using a single parameter set and provides insights into the recovery behavior of HC-induced defects. We find no correlation between bond dissociation and passivation energies and observe that the repeated HC stress and anneal cycles suppress the low energies from the distribution of bond passivation energies, changing its shape from the Gaussian to a non-Gaussian form. [ABSTRACT FROM AUTHOR]

We present a defect spectroscopy technique to profile the energy and spatial distribution of defects within a material stack from leakage current (${J}$ – ${V}$), capacitance (${C}$ – ${V}$), and conductance (${G}$ – ${V}$) measurements. The technique relies on the concept of sensitivity maps (SMs) that identify the bandgap regions, where defects affect those electrical characteristics. The information provided by SMs are used to reproduce ${J}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data measured at different temperatures and frequencies by means of physics-based simulations relying on an accurate description of carrier-defect interactions. The proposed defect spectroscopy technique is applied to ZrO2-based metal–insulator–metal structures of different compositions for dynamic random-access memory capacitor applications. The origin of the observed voltage, temperature, and frequency dependencies of the ${I}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data is understood, and the atomic structure of the relevant stack defects is identified. [ABSTRACT FROM AUTHOR]

Low-power circuits are important for many applications, such as Internet of Things. Device variations and fluctuations are challenging their design. Random telegraph noise (RTN) is an important source of fluctuation. To verify a design by simulation, one needs assessing the impact of fluctuation in both driving current $\Delta {I}_{d}$ and threshold voltage $\Delta {V}_{\textsf {th}}$. Many early works, however, only measured RTN-induced $\Delta {I}_{d}$. $\Delta {V}_{\textsf {th}}$ was not directly measured because of two difficulties: its average value is low and it is highly dynamic. Early works often estimated $\Delta {V}_{\textsf {th}}$ from $\Delta {I}_{d}/{g}_{m}$ (${V}_{g} = {V}_{\textit {dd}}$), where ${g}_{m}$ is the transconductance, without giving its accuracy. The objective of this paper is to develop a new Trigger-When-Charged (TWC) technique for directly measuring the RTN-induced $\Delta {V}_{\textsf {th}}$. By triggering the measurement only when a trap is charged, measurement accuracy is substantially improved. It is found that there is a poor correlation between $\Delta {I}_{d}/{g}_{m}$ (${V}_{g} = {V}_{\textit {dd}}$) and the directly measured $\Delta {V}_{\textsf {th}}$ (${V}_{g} = {V}_{\textsf {th}}$). The former is twice of the latter on average. The origin for this difference is analyzed. For the first time, the TWC is applied to evaluate device-to-device variations of the directly measured RTN-induced $\Delta {V}_{\textsf {th}}$ without selecting devices. [ABSTRACT FROM AUTHOR]

Operating temperature has a significant imp-act on the reliability of metal–oxide–semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ($\Delta {N}_{\text {eff}}$) at operating condition typically shows an Arrhenius temperature dependence with ${E}_{\text {A}}$ ~ 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77–373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture–emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total $\Delta {V}_{\text {th}}$ measured in bias-temperature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process. [ABSTRACT FROM PUBLISHER]

To predict the negative bias temperature instability (NBTI) toward the end of pMOSFETs’ ten years lifetime, power-law-based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to ten years. The objective of this paper is to find how to make n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps, a new method is proposed to capture the generated defects (GDs) in their entirety. n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under ac operation, the model predicts that the GD can contribute to ~90% of NBTI at ten years. [ABSTRACT FROM PUBLISHER]

Using our physics-based model for hot-carrier degradation (HCD), we analyze the temperature behavior of HCD in nMOSFETs with a channel length of 44 nm. It was observed that, contrary to most previous findings, the linear drain current change ( \Delta I\mathrm {d,lin} ) measured during hot-carrier stress in these devices appears to be lower at higher temperatures. However, the difference between the \Delta I\mathrm {d,lin} values obtained at different temperatures decreases as the stress voltage increases. This trend is attributed to the single-carrier process of Si–H bond rupture, which is enhanced by the electron–electron scattering. We also consider another important modeling aspect, namely, the vibrational life-time of the Si–H bond, which also depends on the temperature. We finally show that our HCD model can successfully capture the temperature behavior of HCD with physically reasonable parameters. [ABSTRACT FROM PUBLISHER]

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 ^\circC ; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev , when neutral, lift well above Ev after charging, and return below Ev following neutralization. [ABSTRACT FROM PUBLISHER]

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG\sim VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism. [ABSTRACT FROM PUBLISHER]

Positive charges (PCs) in gate dielectric shift the threshold voltage and cause a time-dependent device variability. To assess their impact on circuits, it is useful to know their distribution for a wide energy range both within and beyond silicon bandgap. Such a distribution is still missing, and a technique for its extraction has not been demonstrated yet. The central objective of this paper is, for the first time, to develop a new fast technique and to demonstrate its capability for probing the energy distribution of PCs over such a wide energy range. Results show that PCs can vary significantly with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps that are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence-band edge are from created defects. The PCs within the bandgap have a peak near Ev + 0.8 eV and saturate for either longer stress time or higher stress temperature. In contrast, the PCs above a conduction band edge, namely the antineutralization positive charges, do not saturate, and their generation is clearly thermally accelerated. [ABSTRACT FROM AUTHOR]

Defects in gate oxide cause breakdown and shorten device lifetime. Early works mainly focused on generation process that converts a precursor into a charged defect. Although it can be neutralized through “recovery,” the defect is still there and will recharge when resuming stress. Recently, we have shown that this is not always the case and some defects can be lost, but a detailed investigation is missing. The central objective of this work is to accurately define and extract the loss, separate it from slowdown, and evaluate their enhancement of device lifetime. Loss is defined as elimination of defects, while slowdown means that recharging a “hardened” precursor takes longer than charging a fresh one. Clear evidences show that losses originate from permanent components, i.e., generated interface states and antineutralization positive charges, while slowdown occurs to both permanent and recoverable components. Loss is thermally accelerated, but slowdown of recoverable component is not. This improved understanding adds slowdown and losses to the existing framework for defects. For the first time, we report that the losses and slowdown enhance device lifetime by a factor of 2.6–4.3, for an allowed threshold voltage shift of 20–45 mV. [ABSTRACT FROM AUTHOR]

Bias temperature instability (BTI) is a serious reliability concern for MOS transistors. This paper covers theoretical analysis, Monte Carlo simulation, and experimental investigation of the charge trapping component of BTI. An analytical model for both stress and recovery phases of BTI is presented. Furthermore, the model properly describes device behavior under periodic switching, also called AC-BTI or cyclostationary operation. The model is based on microscopic device physics parameters, which are shown to cause statistical variation in transistor BTI behavior. It is shown that a universal logarithmic law describes the time dependence of charge trapping in both stress and recovery phases, and that the time dependence may be separated from the temperature and bias point dependence. Analytical equations for the statistical parameters are provided. The model is compared with experimental data and Monte Carlo simulation results. [ABSTRACT FROM AUTHOR]