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A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias ( V\mathrm{ G} )/positive drain bias ( V\mathrm{ D} ) in amorphous hafnium-indium–zinc-oxide thin-film transistors. Negative threshold voltage ( V\mathrm {\mathbf {th}} ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of ( V\mathrm{G}= -5 V, V\mathrm{D}= 15 V, and V\mathrm{ S}= 0 V) and ( V\mathrm{G}= -5 V, V\mathrm{D}= 0 V, and V\mathrm{S}= 15 V) under light illumination, it is found that the negative V\mathrm {\mathbf {th}} shift is affected only by V\mathbf {G} , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by V\mathrm{D} -induced drain-side trapped holes. Furthermore, the drain-side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance ( C\mathrm {\mathbf {GD}} ) was measured before/after the ( V\mathrm{G}= -5 V, V\mathrm{D}= 15 V, and V\mathrm{S}= 0 V) stress to clarify the presence and distribution of the drain-side trapped holes. From C\mathrm {\mathbf {GD}} stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress. [ABSTRACT FROM AUTHOR]

A comprehensive study was done regarding stability under simultaneous stress of light and negative gate dc bias in amorphous hafnium–indium–zinc-oxide ( \alpha -HIZO) thin-film transistors. A negative threshold voltage ( V_{\mathrm{ th}}) shift and an anomalous hump were observed in transfer characteristics after the stress, and it is explained that these phenomena are caused by the hole trapping in the SiO2 gate insulator, not by interface state generation. Furthermore, capacitance–voltage ( C_{G} – VG) measurements were performed with various frequencies to investigate the vertical distribution of the trapped holes in the gate insulator. As a result, the correlation between the vertical location of the trapped holes and the influence on CG – VG characteristics were revealed clearly. First, at the beginning of the stress, photogenerated holes are mainly trapped at the \alpha -HIZO/SiO2 interface and interfacial SiO2 in contact with the interface, which induces the negative V_{\mathrm{ th}} shift. Second, as the stress time increases, the holes start to be trapped in the spatially deeper insulator, which leads to an additional hump in the C_{G}$ – VG characteristics at sufficiently low frequencies. [ABSTRACT FROM AUTHOR]

For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium–indium–zinc–oxide (\alpha-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (Vth) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in \SiO2 at the edge regions along the channel length/width directions and that a negative Vth shift is derived from hole trapping in the gate insulator far from the \SiO2/\HIZO interface. [ABSTRACT FROM AUTHOR]

Negative bias-induced instability of amorphous hafnium indium zinc oxide (α-HIZO) thin film transistors (TFTs) was investigated at various temperatures. In order to examine temperature-induced effects, fabricated TFTs with different combinations of gate insulator and gate metal were stressed by a negative gate bias at various temperatures. As a result, it is proved that negative bias-induced hole-trapping in the gate insulators and temperature-enhanced electron injection from the gate metals occurs at the same time at all temperatures, and the instability of HIZO TFT is more affected by the dominant factor out of the two mechanisms. [ABSTRACT FROM AUTHOR]

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator. [ABSTRACT FROM AUTHOR]