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Abstract: The effects of UV-ozone treatment on ZnO thin films prepared by using radio-frequency magnetron sputtering are investigated. Decrease in the density of oxygen vacancy as well as increase in the density of oxygen interstitial were inferred from the UV-ozone treated samples. It was also found that a considerable difference in the work function (0.25eV) is induced by UV-ozone treatment implying a shift in Fermi level. This shift was confirmed by capacitance–voltage measurements, which demonstrated that the boundary between the inversion region and the depletion region of a ZnO-based metal-oxide-semiconductor (MOS) capacitor positively shifts when UV ozone treated. Our results clearly indicate that the threshold voltage of a thin film transistor can be adjusted by modifying the ZnO surface via UV ozone treatment. MOS capacitors fabricated with UV-ozone treated HfO2 and/or ZnO also yielded a smaller leakage current (~73%–90% smaller) and a larger breakdown voltage (~8%–11% larger). The physical mechanism behind the effect of the UV ozone treatment is addressed in this study with the help of X-ray photoelectron spectroscopy and ultraviolet photoelectron spectroscopy. [Copyright &y& Elsevier]

Pentacene organic thin‐film transistor (OTFT) with HfYO as gate dielectric has been fabricated at room temperature on adhesive flexible vacuum tape and shows high performance. The threshold voltage is as low as −1.77 V due to the high‐κ gate dielectric employed. A small sub‐threshold swing (SS) of 0.145 V/dec indicates good interface between the gate dielectric and pentacene film. Atomic force microscopy (AFM) reveals that large pentacene gains form on the HfYO gate dielectric, leading to a high carrier mobility of 0.236 cm2V−1s−1. These good results suggest that the adhesive vacuum tape can be used as the substrate for adhesive flexible OTFT, and HfYO is a promising gate dielectric for high‐performance pentacene OTFT. [ABSTRACT FROM AUTHOR]

[Display omitted] • Plasmon-phonon resonance is experimentally demonstrated in thin-film transistors. • It is observed for transistors with 2 different high-permittivity gate dielectrics. • It occurs when gate-electrode plasmon and dielectric phonon have close frequencies. • It enhances remote phonon scattering of gate dielectric to degrade channel mobility. The resonance between the plasmons in gate electrode and the phonons in gate oxide of the omnipresent metal–oxidesemiconductor devices predicted in 2004 is experimentally demonstrated to degrade the mobility of the carriers in the semiconductor channel. By using bottom-gated pentacene organic thin-film transistors fabricated on n-type Si substrates with different resistivities, this work experimentally shows that even for thick HfLaO gate dielectric (~50 nm), the interaction between the gate plasmons and the dielectric phonons can significantly affect the carrier mobility. FTIR and Raman spectra reflect that the phonon frequency of the dielectric ranges from 13.2 to 24.9 THz, overlapping the gate-plasmon frequency (13.2 ~ 18.7 THz) of the 0.01 ~ 0.015 Ω·cm substrate. Therefore, the predicted mobility reduction can be explained by a simpler concept of "resonance": when the oscillations of gate carrier and dielectric atom have about the same frequency, the remote phonon scattering of the gate dielectric on the channel carriers is greatly enhanced to reduce their mobility. In summary, this resonance-induced mobility reduction could pose a temperature-related reliability problem to electronic circuits when carrier freeze-out at low working temperature reduces the carrier density in the gate electrode to about 3 × 1018 cm−3 to result in a plasmon frequency close to the phonon frequency of the gate dielectric. [ABSTRACT FROM AUTHOR]

Abstract The effects of source/drain (S/D) electrode material (Ni, Pt and Pd) and deposition method (electron-beam evaporation and sputtering) on the performance of pentacene organic thin-film transistor (OTFT) are studied. Experimental results show that the OTFT with Pd S/D electrodes deposited by sputtering exhibits the best electrical performance. This should be due to the small charge-injection barrier at the pentacene/electrode interface and small thermal load generated during the metal deposition. Besides, through varying the Pd S/D electrode thickness, it is found that increasing the electrode thickness results in performance degradation due to degraded pentacene/electrode interface, which is caused by higher thermal stress developed during longer deposition time. Hightlights • Effect of source/drain (S/D) electrode material is investigated. • Impact of S/D electrode preparation method is studied. • Influence of S/D electrode thickness is discussed. [ABSTRACT FROM AUTHOR]