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In this work, nitrogen‐doped zinc‐tin‐oxygen (ZnSnO:N) optoelectronic synaptic thin film transistors (TFTs) with superior visible light response are fabricated. Nitrogen doping narrows the bandgap of ZnSnO, which in turn broadens the absorption spectrum. Additionally, the reduction of non‐radiative centers in the channel layer prolongs the lifetime of the photogenerated electrons, resulting in enhancements to the photo response throughout the visible region. Optoelectronic synaptic devices based on ZnSnO:N TFTs can accurately replicate synaptic behaviors, including short‐term plasticity (STP) and long‐term plasticity (LTP). Furthermore, the ZnSnO:N optoelectronic synaptic TFT‐based array has the potential to improve image contrast. The ZnSnO:N TFT exhibits a considerable improvement in both visible light photosensitivity and synaptic plasticity. [ABSTRACT FROM AUTHOR]

In this article, this research demonstrates the influence of in-situ introduction of H2 into the working gas on the physical properties of post-annealed In2O3 thin films and the performance of associated devices. A gradual increase in the H2 ratio leads to improved film quality, as indicated by spectroscopic ellipsometry, X-ray photoelectron spectroscopy, and atomic force microscope analyses showing a reduction in defect states such as band-tail states and VO in the film, and a smoother surface morphology with the root mean square roughness approximately 0.446 nm. Furthermore, this hydrogen doping effect results in a distinct shift in the device's threshold voltage toward the positive direction, and an improvement in the field-effect mobility and subthreshold swing. Consequently, a high-performance In2O3:H TFT is developed, exhibiting a field-effect mobility of 47.8 cm2/Vs, threshold voltage of −4.1 V and subthreshold swing of 0.25 V/dec. These findings highlight the potential of in-situ H doping as a promising approach to regulate In2O3-based TFTs. [ABSTRACT FROM AUTHOR]

Amorphous oxide semiconductor thin‐film transistors (AOS TFTs) are ever‐increasingly utilized in displays. However, to bring high mobility and excellent stability together is a daunting challenge. Here, the carrier transport/relaxation bilayer stacked AOS TFTs are investigated to solve the mobility‐stability conflict. The charge transport layer (CTL) is made of amorphous In‐rich InSnZnO, which favors big average effective coordination number for all cations and more edge‐shared structures for better charge transport. Praseodymium‐doped InSnZnO is used as the charge relaxation layer (CRL), which substantially shortens the photoelectron lifetime as revealed by femtosecond transient absorption spectroscopy. The CTL and CRL with the thickness suitable for industrial production respectively afford minute potential barrier fluctuation for charge transport and fast relaxation for photo‐generated carriers, resulting in transistors with an ultrahigh mobility (75.5 cm2 V−1 s−1) and small negative‐bias‐illumination‐stress/positive‐bias‐temperature‐stress voltage shifts (−1.64/0.76 V). The design concept provides a promising route to address the mobility‐stability conflict for high‐end displays. [ABSTRACT FROM AUTHOR]

High‐performance bilayer In2O3/IGZO thin‐film transistors (TFTs) fabricated by pulsed laser deposition are reported. The TFTs exhibit an on/off current ratio of 109, a reversed subthreshold slope (ss) of 0.08 V dec−1, and a high saturation mobility of 47.9 cm2 V−1 s−1. The reliability of the mobility values is critically validated and assessed by four‐probe measurements, the transfer‐length method, and the temperature‐dependence. X‐ray photoelectron spectra are combined with C–V measurements to characterize the interface, and the results show that a two‐dimensional electron gas (2DEG)‐like state accumulates at the In2O3/IGZO interface. However, this state only forms in the subthreshold region and does not cause the high carrier mobility in the region above the threshold. Instead, the enhanced carrier mobility results from the intrinsic high mobility of the In2O3, the smooth surface, and the low‐defect states in the In2O3/IGZO bilayer with a good percolation transport path. [ABSTRACT FROM AUTHOR]

It is difficult to implement high-resolution layer-to-layer alignment by direct inkjet printing because of the limitation of position accuracy of the common inkjet printer. The poor alignment of conventional printers generally causes large parasitic overlap capacitances between the gate and source/drain (S/D) of thin-film transistors (TFTs), which degrades device operating speeds. In this paper, a self-aligned method was proposed to minimize the parasitic overlap capacitance. In this method, a hydrophobic fluoropolymers (Cytop) coffee stripe prepared by inkjet printing was utilized to define the gate electrodes, and to dewet deposited ink droplet for self-aligned S/D electrodes. This kind of inkjet-printed self-aligned TFTs with In0.95Sc0.05Ox channel layer have a parasitic overlap capacitance as small as 0.31–0.45 pF. The TFTs in array exhibited an on/off ratio larger than $\textsf {10}^{\textsf {7}}$ and a maximum saturation mobility of $\textsf {4.63}\,\,\textsf {cm}^{\textsf {2}}\,\,\textsf {V}^{-\textsf {1}}\textsf {s}^{-\textsf {1}}$. [ABSTRACT FROM AUTHOR]

Chitosan (CS) dielectrics are in favor of packed CuI films with tiny grains on them under a robust ambient conditions, and hence facilitate transparent and flexible p-type CuI thin-film transistors with high mobility and on/off current ratio. Complementary inverters based on the CuI transistors demonstrate a voltage gain over 20. [Display omitted] • Flexible/transparent p-Type CuI TFTs are constructed, with μ FE up to 65 cm2V−1s−1 and I on / I off of 104. • Chitosan dielectrics facilitate easy coating of high-quality CuI films under permissive conditions. • Complementary inverters are demonstrated by combining p-type CuI and n -type ITO TFTs. High-performance transparent and low-process-temperature p-type devices are essential for portable and 'invisible' electronics. In this work, high-performance p-channel copper iodide (CuI) thin-film transistors (TFTs) with a bottom-gate structure are achieved via replacing traditional SiO 2 dielectric with Chitosan (CS, a kind of solid polymer electrolytes), with the threshold voltage down to −0.35 V, field-effect mobility (μ FE) up to 60 cm2V−1s−1 and on/off current ratio (I on / I off) beyond 103. The CuI films spin-coated on CS-dielectrics in the air with high humidity have smoother surface morphology, tinier grains, higher packing density and hence a higher μ FE , in sharp contrast with the SiO 2 case. In addition, the CuI films on CS-dielectrics demonstrate a work function ∼ 0.1 eV lower than that on SiO 2 , which implies a smaller hole concentration and higher I on / I off. And the low process temperature (<50 °C) facilitates the achievement of flexible and transparent CuI TFTs with μ FE and I on / I off comparable to those on rigid InSnO (ITO) glass. Furthermore, complementary inverters composed of p-type CuI and n -type ITO TFTs are demonstrated with clear inverting characteristics and voltage gain of over 20. [ABSTRACT FROM AUTHOR]

Fully transparent InZnO thin-film transistors (TFTs), with either a bottom gate or an in-plane gate device structure, were fabricated using the solution-processed SA proton conducting films as gate dielectrics. The self-assembled InZnO channel with different thickness by the gradient shadow mask was fabricated during the same batch radio-frequency magnetron sputtering. The threshold voltage can be modulated from −0.25 to +0.12 V and from −0.07 to +0.25 V by the channel layer thickness variations for the vertically-coupled and laterally-coupled InZnO TFTs, respectively. Accordingly, these InZnO TFTs can operate in either depletion or enhancement mode on the same chip. A general expression of the turn-on voltage in relation to the channel thickness is derived. The device performance with an on/off current ratio of ≥1.5 × 106, a subthreshold swing of down to 70 mV/decade, and a field-effect mobility of up to 34.3 cm2/V · s is exhibited. Our results demonstrate that the same batch channel processing is potentially applied in logic circuits or functional electronics. [ABSTRACT FROM AUTHOR]