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We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9 \times 10^\mathrm \mathbf 7 and 4.2 \times 10^\mathrm \mathbf 7 , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics. [ABSTRACT FROM AUTHOR]

In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of −2.3–1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability. [ABSTRACT FROM AUTHOR]

In this paper, high-performance InGaZnO (IGZO) thin-film transistors were fabricated with film-profile-engineering scheme. The impacts of gate dielectric, O2/Ar ratio during the sputtering of the IGZO, and annealing ambient on the device performance were investigated. It is found that the turn-ON voltage of the device is closely related to the gate dielectric material. For the devices with Al2O3 as the gate dielectric, decent performance in terms of high ON/OFF current ratio (> 10^\mathrm \mathbf 8 ), extremely steep subthreshold swing (62 mV/decade), and good mobility (19.8 cm2/V $\cdot $ s) is obtained. The influences of O2/Ar flow ratio are distinct for the devices with Al2O3 gate oxide. Significant improvement in the stability of the devices to the environment is achieved with the anneal done in a low-pressure N2 ambient. [ABSTRACT FROM PUBLISHER]

100-nm indium–gallium–zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal Al2O3 gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio (>10^7) and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement. [ABSTRACT FROM AUTHOR]

A novel approach, which can delicately form a desirable film profile for deposited gate oxide, channel, and source/drain contacts of oxide-based thin-film transistors (TFTs) is proposed. To demonstrate the film-profile engineering concept used in this approach, a simple one-mask process was developed for fabricating ZnO TFTs with submicrometer channel length. The fabrication takes advantage of a suspended bridge hanging across the device to tailor the desirable profile of deposited films with proper tools. The fabricated devices show high on/off current ratio (>10^9) , steep subthreshold swing (71–187 mV/decade), and high mobility (21–45 cm^2/V\cdot~s ). Very small variation in device characteristics among the devices with the same channel dimensions is also confirmed. [ABSTRACT FROM AUTHOR]

In this letter, we present the high-frequency performances of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a nominal gate length of 0.22 \mum. Owing to the short gate length and adoption of salicide process, cutoff frequency (fT) of 17 GHz and maximum oscillation frequency of \sim21~GHz are obtained. The result suggests that the poly-Si TFT technology is applicable to RF integrated circuits up to 2 GHz. In addition, we also investigate the effects of channel thickness on the high-frequency characteristics of poly-Si TFTs. We find that the variation of fT with channel thickness is mainly due to the change in transconductance. [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices. [Copyright &y& Elsevier]