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In this work, the polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with double gates and nanosheet (NSH) channel structures were fabricated to investigate the impact of NSH channel thickness (tSi) ranging from 15 nm to 2 nm on device performance and reliability. Thinning tSi from 15 nm to 10 nm resulted in improved control of channel potential by the gate voltage, leading to a decreased threshold voltage (VTH) and subthreshold swing (SS). However, further reduction of tSi to 5 nm, while continuing to decrease SS, caused an increase in VTH due to the grain size reduction and quantum confinement (QC) effects. Lastly, reducing tSi to 2 nm resulted in an increase in both SS and VTH mainly due to the QC effect. In terms of reliability, under a fixed positive gate bias stress condition, thinning tSi enhanced the electric field stress, leading to more severe device damage. However, due to the enhanced ability of gate voltage control over the channel potential and the buried channel effect on electron transport resulting from thinning the channel thickness, there exists an optimal range between 10 nm and 5 nm for the selection of tSi in terms of the degradation of VTH, SS, and on-state current. Consequently, it is evident that for transistors utilizing NSH channels, the selection of tSi is not a case of “the thinner, the better.” This finding highlights the need to consider the optimal tSi range between 10 nm and 5 nm, balancing the performance and reliability aspects of the device design. [ABSTRACT FROM AUTHOR]

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance (${G}_{m\_{}{\text {max}}}$) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage (${V}_{\text {BG}}$) operation mode, the ${V}_{\text {BG}}$ can provide a wide threshold voltage (${V}_{\text {TH}}$) tuning range ~2 V when the ${V}_{\text {BG}}$ is modulated from 0 to −4 V. The negative ${V}_{\text {BG}}$ bias stress would induce electron injection from the BG, resulting in positive ${V}_{\text {TH}}$ shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative ${V}_{\text {BG}}$ stress, using ${V}_{\text {BG}}$ to modulate the ${V}_{\text {TH}}$ of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent ${V}_{\text {BG}}$ to adjust the ${V}_{\text {TH}}$ of the JL-TFTs to meet the multiple- ${V}_{\text {TH}}$ requirement of advanced integrated circuits. [ABSTRACT FROM AUTHOR]

In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage ($V_{\text {TH}}$) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to −0.82 V, respectively. The degradation of on-state current is also improved significantly from −87% to −40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step $V_{\text {TH}}$ shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C. [ABSTRACT FROM AUTHOR]

The impacts of ammonia gas (NH3) plasma treatment on the performance and positive gate bias stress (PGBS) of polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) are studied. A −0.785-V threshold voltage ($V_{\mathrm {TH}}$) shift of JL-TFT due to the NH3 plasma treatment is observed, which is attributed to the fixed oxide charge effect of the plasma-induced interfacial layer (PIL). In addition, the transconductance of JL-TFT with the NH3 plasma treatment is enhanced by ~2.73 times due to the trap state passivation of grain boundaries in the poly-Si, and the ON-state current ($I_{\mathrm {ON}}$) is enhanced by ~2.91 times. In addition to the performance enhancement of JL-TFT by the plasma process, the $V_{\mathrm {TH}}$ shift of poly-Si JL-TFT under PGBS is suppressed from −0.240 to −0.063 V after the plasma treatment. It is attributed to the less degradation of insulator/channel interface due to the growth of PIL by the plasma process. Moreover, the $I_{\mathrm {ON}}$ degradation of JL-TFT after PGBS is also improved from −19% to −16% after the plasma treatment. As the carrier transport of JL-TFT is the bulk conduction rather than the surface conduction of conventional inversion-mode TFT, the degradation of insulator/channel interface would exhibit less impacts on the $I_{\mathrm {ON}}$. The improvement of performance and PGBS of JL-TFT by the NH3 plasma treatment would be beneficial to the application of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

In this paper, the positive and negative bias temperature instability (P/NBTI) of complementary metal–oxide–semiconductor (CMOS) low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO 2 gate dielectric are studied simultaneously. Significant threshold voltage shift Δ V TH , degradation of the subthreshold swing S.S. and transconductance G m are observed for both n-type LTPS-TFTs after PBTI stress and p-type LTPS-TFTs after NBTI stress. Moreover, the G m degradation rate with the stress time of p-type devices during NBTI shows significantly different behavior from the PBTI of n-type devices. The PBTI of n-type device shows a saturation behavior of the G m degradation with various stress bias and temperature. Conversely, the NBTI of p-type device shows an enhanced G m degradation rate with the increase of stress time and stress temperature. In addition, the threshold voltage shift |Δ V TH | of PBTI does not obey the traditional empirical power law model, but the NBTI obeys it with higher time exponent. Consequently, the NBTI of the p-type device shows worse driving current I drv degradation than the PBTI of the n-type device mainly due to the different G m degradation behavior. [ABSTRACT FROM AUTHOR]

In this paper, the opposite impacts of N2O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N2O plasma surface treatment is observed, including threshold voltage reduction \Delta V\mathrm {\mathbf {TH}}\sim -0.57 V, 1.55× higher transconductance G\mathit {m} , and 1.82× higher driving current I{\rm{drv}} . However, p-channel LTPS-TFT shows serious performance degradation after N2O plasma surface treatment, including threshold voltage increase \Delta V\mathrm {\mathbf {TH}}~\sim -0.99 V, transconductance G\mathit {m} reduction, and driving current I\mathrm {\mathbf {drv}} degradation. The difference of the two mechanisms of N2O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N2O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit. [ABSTRACT FROM PUBLISHER]

• P-type tunnel transistors with different gate capacitance are demonstrated. • Tunnel transistors with HfZrO2 gate dielectric is studied. • Tunnel transistors show stronger gate capacitance effect than general transistors. In this work, the polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors (TFETs) with TiN/HfZrO 2 gate stack materials are demonstrated to exhibit low threshold voltage ~ –1.218 V, subthreshold swing (SS) ~ 0.311 V/decade and channel length insensitive transfer characteristics. Conventional carrier transport mechanism of poly-Si thin-film transistors (TFTs) is the thermionic emission with scattering effect, which is deduced as the drift-diffusion transport model with additional trap state induced energy barrier height, resulting in the stronger channel length dependence effect. For the poly-Si TFETs, the carrier transport mechanism is the interband tunneling, including band-to-band tunneling and trap-assisted tunneling, which is less affected by the channel length. The different carrier transport mechanisms of poly-Si TFETs and TFTs would lead to different gate dielectric thickness effect. When the thickness of gate dielectric HfZrO 2 is reduced from 18 to 10 nm to increase the gate capacitance density, the SS and on-state current of poly-Si TFETs exhibit much higher improvement than them of poly-Si TFTs. It indicates that the high gate capacitance density is a key parameter for the development of poly-Si TFETs to replace the conventional poly-Si TFTs in three-dimensional integrated circuit applications. [ABSTRACT FROM AUTHOR]