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We investigate the temperature dependence of the hysteresis in the transfer characteristics of 4H silicon carbide (4H-SiC) lateral MOSFETs. Within temperatures ranging from 150 to 300 K, we experimentally characterize the hysteresis width as the difference of the threshold voltage between up and down sweeps. We observe a considerable increase in the hysteresis width toward lower temperatures. When the gate voltage sweeps up, the threshold voltage shifts toward positive gate voltages. This shift is maintained even during the subsequent down sweep. We attribute this behavior to acceptor-like border traps, which get more negatively charged at higher gate voltages. These traps are presumably located near the SiC/SiO2 interface with energy levels close to the SiC conduction band edge. Using a two-state non-radiative multi-phonon model, we calculated capture and emission times to show that the hysteresis width corresponds to the charge stored on these traps and, hence, possesses an intrinsic temperature dependence due to the transition barriers. [ABSTRACT FROM AUTHOR]

We present time-zero characterization and an investigation on bias temperature instability (BTI) degradation between 4 and 300 K on large area high- ${k}$ CMOS devices. Our measurements show that negative BTI (NBTI) on pMOSFETs freezes out when approaching cryogenic temperatures, whereas there is still significant positive BTI (PBTI) degradation in nMOSFETs even at 4 K. To explain this behavior, we use an efficient implementation of the quantum mechanical nonradiative multiphonon charge trapping model presented in Part I and extract two separate trap bands in the SiO2 and HfO2 layer. We show that NBTI is dominated by defects in the SiO2 layer, whereas PBTI arises mainly from defects in the HfO2 layer, which are weakly recoverable and do not freeze out at low temperatures due to dominant nuclear tunneling at the defect site. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) MOSFETs still exhibit higher drifts of the threshold voltage than comparable silicon devices due to charge trapping, especially regarding small time scales. Understanding this behavior and the consequences in application relevant conditions is therefore of high research interest. Since charge trapping at different defects close to the SiC/ SiO2 interface and in the bulk oxide is strong bias and temperature-dependent, the phenomenon is referred to as bias temperature instability (BTI). It has been shown that drifts caused by BTI vary both in transient shape and magnitude for commercially available devices. These differences arise from defect densities and properties in the respective technologies. A physical model together with defect parameters that explain the charge transfer reactions at the defects is essential to understand all peculiarities of the transient degradation. In this work, we use a novel method to semiautomatically extract defect parameters within a two-state nonradiative multiphonon model framework. Our work reveals properties of defects responsible for shifts of the threshold voltage for both short-term ac and long-term dc stress conditions which are accurately reproduced for three different DMOS technologies. Our calibrated simulation framework is further used to extrapolate device degradation at operation relevant ac bias conditions to typical device lifetimes. [ABSTRACT FROM AUTHOR]

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit's performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too. [ABSTRACT FROM AUTHOR]

In nMOS transistors the impact of positive bias temperature instability (PBTI) on the device performance is typically considered negligible and has thus been barely studied in the past. However, an accurate description of this phenomena requires and in depth understanding of the physical origin being responsible for the change of the device characteristics over time. For the assessment of PBTI in nanoscale SiON nMOS transistors we make use of the time-dependent defect spectroscopy (TDDS) and examine the device performance degradation at the single-defect level. Contrary to what is visible in large-area devices, our investigations clearly reveal that charge trapping at both electron and hole traps contributes to the overall drift of the threshold voltage in these devices. Furthermore we observe that hole traps account for around 20% of the total threshold voltage drift. To evaluate the impact of single-defects on the device performance we characterize the charge trapping kinetics of a number of defects, which can be explained by employing a two-state defect model. In our approach we observe charge trapping due to defect/channel interaction for electron traps and defect/gate interaction for hole traps. The extracted trap levels and trap depths clearly reveal that the electrically active electron traps reside closer to the SiON/Si interface while the hole traps are located closer to the poly-Si/SiON interface. Finally, the extracted trap parameters are fully consistent with defect candidates for electron and hole trapping from DFT calculations. [ABSTRACT FROM AUTHOR]

To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed. [ABSTRACT FROM AUTHOR]

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO 2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies. [ABSTRACT FROM AUTHOR]

One of the main drawbacks of the continuous scaling of MOS transistors is the increase in variability of the device characteristics, e.g. threshold voltage, SS, mobility, which represents a formidable challenge for robust electronic circuits. Device variability issues are categorized into contributions from time-zero threshold voltage variations, as well time-dependent effects, i.e. variability in the drift of the threshold voltage. The time-dependent effect is a consequence of charge trapping at electrically active defects located inside the insulator or at the insulator/semiconductor interface as well as the creation of new defects. Furthermore, the defects appear statistically distributed in terms of their number and trap location which can lead to immediate failure of devices and circuits for unfortunate combinations (killer defects) which becomes increasing critical for nanoscale nodes. In this work, we thoroughly investigate the distribution of the contribution of the defects on the device behavior. Our results provide a simple mathematical expression to link device geometry and variability. Furthermore, by combining single-defect analysis with a defect-centric model our approach enables us to accurately extract valuable information about the time-dependent variability for a whole technology. While existing approaches focus on either large-area or nanoscale nodes, our model holds for both regimes and is of high relevance for the optimization of circuits towards high immunity against charge trapping. • Investigation of the distribution of the contribution of the defects on the device behavior. • Single-defect analysis enables the accurate extraction of valuable information about the time-dependent variability for a whole technology. • Demonstrating that the scaling of statistical parameters measured at V th can be described better with a W × √L trend rather than the area of the devices W × L. [ABSTRACT FROM AUTHOR]

Bias temperature instability (BTI) and soft errors are major reliability concerns for deep submicron technologies. Negative BTI leads to an increase of the threshold voltage of PMOS transistors and is thus considered a serious challenge for improving circuit performance. In this paper, we concentrate on a design-time solution, i.e., more reliable NMOS only Schmitt Trigger with Voltage Booster (NST-VB). For this we analyzed the impact of BTI on the soft-error susceptibility of different CMOS circuits using HSPICE and performed critical charge simulations considering different supply voltages and stress time. From our results, we conclude that the NST-VB circuit has a higher critical charge when compared to CMOS inverters and Schmitt trigger (ST) based counterparts. NST-VB has improved the sensitivity of 62.48% and 55.10%, as compared to CMOS inverter and ST circuits, respectively, after three years of operation. To better assess soft error resilience, we introduce a soft error rate ratio (SERR) as a performance metric. Our analysis indicates that NST-VB has 12.62%, and 12.39% less SERR compared to ST and CMOS inverters. The effect of process variation on CMOS inverter, ST inverter and NST-VB circuit are analyzed using 5000 Monte Carlo simulations for critical voltages and we observe that the deviation of NST-VB is 6.06× and 6.89× less as compared to the CMOS and ST based inverters, respectively. • Soft error tolerance analysis of BTI resilient Schmitt trigger circuit has been performed. • Soft error rate with and without BTI stress has been calculated. • Critical charge sensitivity with the stress time for CMOS, Schmitt trigger and NST-VB based inverter circuits has been analysed. • For the process variability analysis on the circuits, 5000 Monte Carlo simulations for the critical voltages has been performed. [ABSTRACT FROM AUTHOR]