Search

It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement. In this study, we design a carry-look-ahead delay chain structure and integrate an interleaved sampling method with an online calibration and bin readjustment approach to implement a TDC. We take advantage of the adaptive logic module units applied in a Cyclone-10 GX (10CX220YF780E5G), which is a 20 nm low-power consumption and low-cost FPGA. In this new generation FPGA, we implemented a high-precision time interval measurement, which exceeded all our previous works with a 4.8 ps root-mean-square resolution and a 5.68 ps least-significant-bit resolution. [ABSTRACT FROM AUTHOR]

Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit. [ABSTRACT FROM AUTHOR]

The method commonly used to produce a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) creates a tapped delay line (TDL) for time interpolation to yield high time precision. We conduct timing adjustment and bin realignment to implement a TDC in the Altera Cyclone-IV FPGA. The former tunes the carry look-up table (LUT) cell delay by changing the LUT’s function through low-level primitives according to timing analysis results, while the latter realigns bins according to the timing result obtained by timing adjustment so as to create a uniform TDL with bins of equivalent width. The differential nonlinearity and time resolution can be improved by realigning the bins. After calibration, the TDC has a 18 ps root-mean-square timing resolution and a 45 ps least-significant bit resolution. [ABSTRACT FROM AUTHOR]