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In this paper, a receiver front-end tailored to Bluetooth Low Energy applications is presented. In the proposed solution, the LNA, mixers, VCO, quadrature scheme and the first stage of the analog base-band share the same bias current under a 0.8 V voltage supply leading to a sub-mW power consumption. A channel selection filter, implemented through a current re-use gm-C topology, completes the design. The presented prototype, realized in 130 nm CMOS technology, occupies an active area of 0.25 mm^2 while consuming only 0.6 mW. With a NF of 15.8 dB, an IIP3 of -17 dBm at the maximum gain and an image rejection above 30 dB the receiver front-end meets BLE noise figure, image rejection, phase noise and linearity requirements. [ABSTRACT FROM PUBLISHER]

This brief presents a flexible gm-C complex filter for Bluetooth-low-energy receivers. Each complex pole is realized sharing a bias current among transconductors, leading to an ultralow-power solution. The filter, which is designed in the 130-nm complimentary metal–oxide–semiconductor technology, has a power dissipation of only 42 μW from a 0.8-V supply voltage. With a center frequency and a passband of 2 and 1 MHz, respectively, the simulated filter provides a rejection of the adjacent channel of 34 dB and a spurious-free dynamic range of 52.7 dB. [ABSTRACT FROM AUTHOR]

An intuitive yet sufficiently accurate formulation of the phase noise of various commonly used oscillators, including most types of class-B (standard, AC-coupled and with tail filter) and class-C, is derived and used to compare their fundamental limitations. A noise factor that represents the difference between the maximum achievable Figure of Merit and the actual one is derived for all topologies considered. Measurements on a dedicated chip prototype that integrates two high performance topologies allow to verify, in an unbiased way, the accuracy of the predictions. A very good agreement between the model and both simulation and measurement is obtained. [ABSTRACT FROM AUTHOR]

A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost constant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switch-pair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal power consumption in the complementary (P-N) configuration is reduced by 75% compared to the single-switch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 nm CMOS 4 GHz DCO prototype show a minimum phase noise of -129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N configuration, and of -134.7 dBc/Hz in the N-only configuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of -185 dBc/Hz. [ABSTRACT FROM AUTHOR]