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Artificial intelligence has been demonstrated for numerous applications including image recognition and processing, internet-of-things (IoT), and speech recognition. Recent neural network (NN) architectures escalating to perform these functionalities require deep-learning and deep NN (DNN) implementation. However, the present algorithm and circuit of DNN suffer from area and energy-efficiency. The usage of an energy-efficient and cost-effective binary NN (BNN) can mitigate the performance bottleneck. The basic component of BNN (the XNOR and accumulate module) is capable of replacing the conventional multiply-and-accumulate (MAC) operation. Among various emerging nonvolatile memories (NVMs), spintronics-based devices are attracting attention for the implementation of the aforementioned architectures. Multilevel voltage-controlled spin-orbit torque -based magnetic memory (MV-SOTM) spin device as synapse and voltage-controlled SOTM (V-SOTM) device as spin-neuron are capable of producing an all-spin NN. This article presents advanced XNOR operation using a computing-in-memory (CiM) mechanism wherein both V-SOTM and MV-SOTM (using series and parallel configuration) based synapses are compared. The MV-SOTM design dissipates 35.51% lesser energy as compared to the 1-bit V-SOTM. Further, the 8-bit synaptic crossbar array is implemented using both the devices with two output spin-neurons. These series and parallel MV-SOTM-based synaptic arrays consume 42.22% and 45.12% lesser power, respectively, as compared to 1-bit V-SOTM based synaptic array. Furthermore, the all-spin BNN design demonstrates a handwritten digit recognition application. [ABSTRACT FROM AUTHOR]

Conventional von Neumann architecture suffers from data trafficking and power hungriness between memory and processing units. Recent architectures escalating to overcome these limitations are near-memory architecture (NMA) and computing-in-memory (CiM) architecture (CMA). Spintronics-based devices, such as spin-transfer torque magnetic memory (STTM), spin-orbit torque magnetic memory (SOTM), differential spin Hall–effect-based magnetic memory (DSHEM), and multilevel voltage-controlled SOT-based magnetic memory (MV-SOTM) are a few promising contenders for post-CMOS technology. MV-SOTM spin device is used in this study to showcase the CMA to perform basic logic operations namely AND/ NAND, OR/ NOR, and XOR/ XNOR within the memory array. Furthermore, magnetic full adder (MFA) is implemented using CMA in MV-SOTM array. The performance of CMA design for MV-SOTM-based MFA is compared with SOTM-based MFA. The proposed CiM design for MV-SOTM-based MFA shows 29.2% and 12.22% performance improvement in terms of write energy and logic power, respectively. Moreover, up to 34% area reduction is achieved in comparison to SOTM-based CiM MFA. [ABSTRACT FROM AUTHOR]

Spintronics, being a burgeoning area of research, aims to incorporate magnetic tunnel junction (MTJ), as a basic storage building block, to various electronic applications. In continuation of many device structure using MTJ such as spin-transfer torque (STT)-MTJ, spin Hall effect (SHE)-MTJ, spin–orbit torque (SOT)-MTJ, domain wall-based MTJ, and complementary polarizer MTJ, this paper presents a differential spin Hall effect (DSHE). The working and operational analysis of the DSHE-based memory element is presented. It provides 50% improved write energy and more than 1.5 times faster read as compared to a single-ended SHE-MTJ. The device structure is well suited for various differential circuit applications, for example, nonvolatile static random access memory (NVSRAM), nonvolatile flip flop (NVFF), magnetic full adder, and nonvolatile differential sense latch, with a fast and energy-efficient operation. In addition, DSHE-MTJ application for NVSRAM (named as DSNVM) is proposed. Performance of DSNVM is compared with the STT+SHE-based NVSRAM (named as SHENVM). DSNVM shows improved performance in terms of area overhead, restoration delay, and energy. DSNVM provides 40% faster restoration and 16.7% lesser energy as compared to SHENVM. Furthermore, a computational investigation for cell stability is depicted using butterfly curve and N-curve methods. Usually, write noise margins deteriorate in NVSRAMs due to the constituent NV cell. However, read as well as write noise margin is improved in DSNVM. [ABSTRACT FROM AUTHOR]

The Computing-in-Memory (CiM) is one of the best solutions to overcome the data transferring limitation between memory and processor. Moreover, spintronics based devices such as spin-transfer torque magnetic memory (STTM) and spin-orbit torque magnetic memory (SOTM) are emerging as viable contenders for CiM applications. SOTM along with their driving CMOS counterparts show a huge reduction in area and add nonvolatility to CiM designs. In this work, energy-efficient CiM working is performed using Voltage-Controlled SOTM (V-SOTM) where logic operations are implemented within the memory array. The operational conditions and working for performing logic within the memory blocks are elaborated in detail. Further, V-SOTM based full adder (FA) for CiM is presented. Performance analysis has been carried out and compared with exiting CMOS, STTM, SOTM based FA. V-SOTM FA shows 53.98% and 2.7% reduction in logic power and data transfer energy, respectively when compared to SOTM based CiM FA. Furthermore, the VCMA voltage variations for V-SOTM FA is carried out that provide performance improvement with varying voltage pulse. Finally, the effect of parametric variations is carried out using Monte Carlo analysis. [ABSTRACT FROM AUTHOR]