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Insulated gate bipolar transistor (IGBT) has been widely used in the voltage-source-converter-based high-voltage direct current (VSC-HVDC). However, the electromagnetic interference (EMI) generated by its fast switching process affects the normal operation of the surrounding power equipment. The switching voltage and current of IGBT are the main sources of EMI. Different driving circuit parameters result in different IGBT switching characteristics. In this article, the switching model of IGBT is introduced first and the influence of driving parameters on EMI sources is analyzed. Based on the conducted EMI experiment platform of an IGBT module, the time-domain waveforms of switching voltage and current under different driving parameters are obtained and compared with the model. Then the interference voltage spectrums are measured by an EMI receiver under different driving parameters. The influence of driving parameters on conducted EMI in 0.15–30 MHz is then analyzed and explained by combining the result of time domain and frequency domain. This article comprehensively analyzes the relationship between driving parameters and EMI sources and summarizes the influence characteristics of driving parameters on common-mode (CM) and differential-mode (DM) noise. The conclusions can help the parameters design of driving board, which can effectively reduce the conducted EMI of the converter. [ABSTRACT FROM AUTHOR]

This article addresses the influence of parameters spread on transient current distribution among parallel-connected silicon carbide (SiC) mosfets and proposes a chips classification method to suppress current imbalance. A comprehensive comparison of parameter spread between silicon (Si) and SiC mosfets is first presented. Then, a new classification criterion, referred to in this article as a distance coefficient of transfer curves (DCTC), is proposed to characterize device spread. In addition, the sensitivity analysis of transient current imbalance (TCI) to device spread is carried out. It is found that TCI increases almost linearly with increasing DCTC. Furthermore, a hierarchical cluster algorithm is developed to achieve an automated chips classification for multiple devices intended for paralleled application. This algorithm may as well facilitate the chip selection process for multiple-chip power module packaging. Moreover, the influence of operating temperature on classification is also discussed. It should be noted that chips classification needs to consider real application conditions and package parasitic. Finally, a test bench with a round layout is designed, to keep circuit layout asymmetry to a minimum, and used to experimentally verify the performance of the classification method. The experimental results validate the effectiveness of the proposed classification method for suppressing TCI. [ABSTRACT FROM AUTHOR]