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A novel high-voltage single-emitter horizontal current bipolar transistor (HCBT) is presented. Breakdown voltage improvement compared to high-speed transistor is obtainedwith full depletion of the intrinsic collectorby using implanted CMOS p-well region. Transistors with \text BV\text {CEO} = {10.5} V and fT = {15.8} GHz are demonstrated. Higher operating currents can be easily obtained by stretching the emitter length resulting in a flexible physical design of circuits. The transistor is fabricated in 0.18- \mu \textm HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks. [ABSTRACT FROM AUTHOR]

The ambipolar-diffusion-with-cutoff (ADC) model is extended to estimate the single-event-induced collected charge for multiple transistors for circuits simulation. The proposed improvement in the model includes both parasitic-bipolar and charge-sharing effects for a given technology. Simulation results indicate excellent agreement between the proposed model and published TCAD data for 130, 90, 65, and 40 nm technology nodes. A comparison between ADC and both rectangular parallelepiped (RPP) and integral rectangular parallelepiped (IRPP) models indicates a 2.7\times and 2.5\times lower error in estimating collected charge when compared with TCAD data. The ADC average error was estimated to be 7.1 fC and for the RPP and IRPP about 19.1 fC and 17.5 fC, respectively, across the technologies for particles with the linear energy transfer range from 1 - 30~\MeV-cm^2/\mg. [ABSTRACT FROM PUBLISHER]

Recent years, the hardening of combinational circuits is becoming a common concern. Unlike the transistor-level hardening technique, the cell-level hardening technique, a divide and conquer strategy, can substantially make use of some typical character in the cell-circuit module to mitigate single event transient (SET) sensitivity. The mirror image (MI) technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure. 3D TCAD mixed-mode simulation have been performed in 65 nm twin-well bulk CMOS process, the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25 %, and can mitigate the SET pulse width from the posterior-stage PMOS about 10 %. The MI technique, a represent of the cell-level technique, may be the future of the hardening of combinational circuits. [ABSTRACT FROM AUTHOR]

A novel RHBD technique that exploits charge sharing is implemented in the single-ended gain stage of a folded-cascode operational amplifier to mitigate single-event transients (SETs). The efficacy of the technique is demonstrated via two-photon laser experiments. Using settling time as the primary metric for SET severity, the proposed layout technique achieves sensitive area reductions ranging from 41% to 95% with an overall area penalty of less than 1%. [ABSTRACT FROM PUBLISHER]

Using three-dimensional technology computer-aided design (TCAD) simulation, parasitic bipolar amplification in a single event transient (SET) current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both 130-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor. [ABSTRACT FROM AUTHOR]

A novel radiation-hardened-by-design (RHBD) technique that utilizes charge sharing to mitigate single-event voltage transients is employed to harden bias circuits. Sensitive node active charge cancellation (SNACC) compensates for injected charge at critical nodes in analog and mixed-signal circuits by combining layout techniques to enhance charge sharing with additional current mirror circuitry. The SNACC technique is verified with a bootstrap current source using simulations in a 90-nm CMOS process. Reductions of approximately 66% in transient amplitude and 62% in transient duration are observed for 60-degree single-event strikes with an LET of 40 MeV*cm^2/mg. [ABSTRACT FROM PUBLISHER]

A novel double-emitter horizontal current bipolar transistor (HCBT) with reduced-surface-field (RESURF) region is presented. The structure is integrated with standard 0.18- \mu m CMOS, together with high-speed HCBT with BV_{\mathbf {CEO}}=3.6 V and double-emitter HCBT with BV_{\mathbf {CEO}}=12$ V. The second RESURF drift region is formed using a standard CMOS p-well implant for the formation of local substrate below the extrinsic collector. Collector-emitter breakdown is completely avoided by the E-field shielding. Breakdown occurs between the collector and the substrate and equals 36 V. The transistor is fabricated in HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks. [ABSTRACT FROM PUBLISHER]