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In solution processed electronic devices it is crucial that the deposited inks are properly aligned and that all post‐processing steps are compliant with each other. Moreover, shorter channel lengths are highly beneficial to increase the device performance. Herein, laser printing of metals and polymer reservoirs allows to print sub‐micrometer sized channel lengths while confining functional inks into these small gaps. Therefore, a manufacturing concept and optimized material stack, suitable for combined inkjet and laser printing are proposed. A nanoparticulate indium oxide (In2O3) semiconductor is inkjet printed into and constrained by a 3D laser written polymer (pentaerythritol triacrylate, PETA) reservoir. Inside the 3D printed polymer reservoir, platinum (Pt) electrodes, that are further routed over the reservoir walls, are laser printed by a metal reduction process. The transistor fabrication is completed by a second inkjet printed layer of composite solid polymer electrolyte and an organic top‐gate layer (PEDOT:PSS). This concept does not exceed annealing temperatures higher than 100 °C, and is compatible with a range of substrates. The characterized electrolyte‐gated field‐effect transistor show a reasonable on/off‐ratio in the range of 104 with negligible leakage currents. This materials and hybrid device manufacturing scheme has believed great potential for bioelectronics, lab‐on‐a‐chip applications and others. [ABSTRACT FROM AUTHOR]

Low-frequency noise is a critical characteristic of transistors, but there are only a few experimental works on the noise in printed electronics. In this work, we characterize the low-frequency noise of inkjet-printed electrolyte-gated thin-film transistors (EGTs) with indium-oxide semiconductors. We confirm that the carrier number fluctuation with correlated mobility fluctuation is the dominating noise generation mechanism. Also, we present the benchmark analysis on the noise level of various thin-film technologies. Notably, the extracted value of trap density near the insulator-channel interface is high, indicating an inferior quality of solution-processed and inkjet-printed thin-films. However, because of electrolyte-gating, the large areal gate capacitance compensates the negative effect of the high trap density, effectively reducing the flat-band voltage noise. As a result, the normalized drain current noise is considerably lower than solution-processed transistors and comparable with sputtered inorganic transistors with dielectric gating. This renders the electrolyte-gating approach useful in reducing the noise for printed/solution-based transistors, suitable for low-noise applications. [ABSTRACT FROM AUTHOR]

Unlike nanoscale silicon transistors, printed thin-film transistors usually rely on micrometer size channel lengths. The device dimensions, the morphology of the channel material, and the interface properties strongly influence important device parameters such as the threshold voltage (Vth) and the transconductance parameter (k). In this article, we analyze and model the dependence of critical electrical device properties of printed, electrolyte-gated transistors, based on crystalline indium oxide channel, for various device geometries. It is shown that the threshold voltage scales with the charge density at the electrolyte channel interface and is hence linearly dependent on the channel length (L). Furthermore, nonlinear scaling effects in the transconductance parameter and in the ON-current are studied, which turn out to be dependent on both, channel width and length. Finally, we present a scaling model capturing the width/length dependencies of the studied transistor technology which enables the correct simulation of logic gates. [ABSTRACT FROM AUTHOR]

Rectifiers are vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode’s p-n-junction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 k Ω. Furthermore, experiments show that the circuit can work with an input amplitude down to 500mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications. [ABSTRACT FROM AUTHOR]

Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead. [ABSTRACT FROM AUTHOR]

In this report, we have studied field-effect transistors (FETs) using low-density alumina for electrolytic gating. Device layers have been prepared starting from the structured ITO glasses by printing the In2O3 channels, low-temperature atomic layer deposition (ALD) of alumina (Al2O3), and printing graphene top gates. The transistor performance could be deliberately changed by alternating the ambient humidity; furthermore, ID,ON/ID,OFF-ratios of up to seven orders of magnitude and threshold voltages between 0.66 and 0.43 V, decreasing with an increasing relative humidity between 40% and 90%, could be achieved. In contrast to the common usage of Al2O3 as the dielectric in the FETs, our devices show electrolyte-type gating behavior. This is a result from the formation of protons on the Al2O3 surfaces at higher humidities. Due to the very high local capacitances of the Helmholtz double layers at the channel surfaces, the operation voltage can be as low as 1 V. At low humidities (≤30%), the solid electrolyte dries out and the performance breaks down; however, it can fully reversibly be regained upon a humidity increase. Using ALD-derived alumina as solid electrolyte gating material, thus, allows low-voltage operation and provides a chemically stable gating material while maintaining low process temperatures. However, it has proven to be highly humidity-dependent in its performance. [ABSTRACT FROM AUTHOR]

Printed and flexible metal-oxide transistor technology has recently demonstrated great promise due to its high performance and robust mechanical stability. Herein, fully printed inverter structures using electrolyte-gated oxide transistors on a flexible polyimide (PI) substrate are discussed in detail. Conductive graphene ink is printed as the passive structures and interconnects. The additive printed transistors on PI substrates show an Ion=Ioff ratio of 106 and show mobilities similar to the state-of-the-art printed transistors on rigid substrates. Printed meander structures of graphene are used as pull-up resistances in a transistor-- resistor logic to create fully printed inverters. The printed and flexible inverters show a signal gain of 3.5 and a propagation delay of 30 ms. These printed inverters are able to withstand a tensile strain of 1.5% following more than 200 cycles of mechanical bending. The stability of the electrical direct current (DC) properties has been observed over a period of 5 weeks. These oxide transistor-based fully printed inverters are relevant for digital printing methods which could be implemented into roll-to-roll processes. [ABSTRACT FROM AUTHOR]

Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor–resistor logic has been employed so far, but depletion- and enhancement-mode EGTs in a transistor–transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~2 × for the gain and oscillation frequency, in comparison with the resistor–transistor logic design. Moreover, the power consumption is reduced by 6 ×. [ABSTRACT FROM AUTHOR]

Printed electronics (PE) circuits have several advantages over silicon counterparts for the applications where mechanical flexibility, extremely low-cost, large area, and custom fabrication are required. The custom (personalized) fabrication is a key feature of this technology, enabling customization per application, even in small quantities due to low-cost printing compared with lithography. However, the personalized and on-demand fabrication, the non-standard circuit design, and the limited number of printing layers with larger geometries compared with traditional silicon chip manufacturing open doors for new and unique reverse engineering (RE) schemes for this technology. In this paper, we present a robust RE methodology based on supervised machine learning, starting from image acquisition all the way to netlist extraction. The results show that the proposed RE methodology can reverse engineer the PE circuits with very limited manual effort and is robust against non-standard circuit design, customized layouts, and high variations resulting from the inherent properties of PE manufacturing processes. [ABSTRACT FROM AUTHOR]

In this study, a facile method to fabricate a cohesive ion‐gel based gate insulator for electrolyte‐gated transistors is introduced. The adhesive and flexible ion‐gel can be laminated easily on the semiconducting channel and electrode manually by hand. The ion‐gel is synthesized by a straightforward technique without complex procedures and shows a remarkable ionic conductivity of 4.8 mS cm−1 at room temperature. When used as a gate insulator in electrolyte‐gated transistors (EGTs), an on/off current ratio of 2.24×104 and a subthreshold swing of 117 mV dec−1 can be achieved. This performance is roughly equivalent to that of ink drop‐casted ion‐gels in electrolyte‐gated transistors, indicating that the film‐attachment method might represent a valuable alternative to ink drop‐casting for the fabrication of gate insulators. [ABSTRACT FROM AUTHOR]

Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology – Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain. [ABSTRACT FROM AUTHOR]

Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V. [ABSTRACT FROM AUTHOR]

Oxide semiconductors have the potential to increase the performance of inkjet printed microelectronic devices such as field-effect transistors (FETs), due to their high electron mobilities. Typical metal oxides are n-type semiconductors, while p-type oxides, although realizable, exhibit lower carrier mobilities. Therefore, the circuit design based on oxide semiconductors is mostly in n-type logic only. Here we present an inkjet printed pn-diode based on p- and n-type oxide semiconductors. Copper oxide or nickel oxide is used as p-type semiconductor whereas n-type semiconductor is realized with indium oxide. The measurements show that the pn-diodes operate in the voltage window typical for printed electronics and the emission coefficient is 1.505 and 2.199 for the copper oxide based and nickel oxide based pn-diode, respectively. Furthermore, a pn-diode model is developed and integrable into a circuit simulator. [ABSTRACT FROM AUTHOR]

Printed electronics can benefit from the deployment of electrolytes as gate insulators, which enables a high gate capacitance per unit area (1– 10 μF cm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedance measurements and separate extrinsic components from the lumped terminal capacitance. The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices. [ABSTRACT FROM AUTHOR]

A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware. [ABSTRACT FROM AUTHOR]

Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation. [ABSTRACT FROM AUTHOR]

Electrolyte-gated field-effect transistor technology is an attractive candidate for printed low-power electronics due to its high field-effect mobility and extremely low-voltage operation. Relying on an additive process, inkjet-printed devices display large process variations due to ink-substrate interactions, sensitivity to environmental conditions, such as temperature and humidity, as well as intrinsic variations of the ink. All of these sources of variations may display themselves in non-Gaussian distributions as suggested by our experiments. In this paper, we therefore propose a generic methodology for variability modeling of printed transistors, based on the Gaussian mixture model, which can be used to model any arbitrary distribution of the transistor model parameters. The proposed methodology was tested on two different data sets and has been used to predict the behavior of a measured printed security circuit as well as transistor dc characteristics. [ABSTRACT FROM AUTHOR]

Printed electronics (PE) is a promising technology that provides mechanical flexibility and low-cost fabrication and the key enabler for emerging applications, such as smart sensors, wearables, and Internet of Things. To use printed batteries or printed energy harvesters in the future, electrolyte-gated field-effect transistors (EGFETs) based on inorganic materials enable printed circuits requiring small supply voltage and low power. Since these applications need secure communication and/or authentication, it is imperative to embed security primitives for cryptographic key and identification purposes into the applications. Physical unclonable functions (PUFs) have been adopted widely to provide secure keys. In this paper, we present the design, simulation, fabrication, and measurements of a PUF based on EGFETs using inorganic inkjet PE. A comprehensive framework, including Monte Carlo simulations calibrated on real device measurements, is developed. Moreover, a multibit PE-PUF design is proposed to optimize area usage. Our simulation results show that the PE-PUF has ideal uniqueness (50.1%) and good reliability (89%). In addition, the proposed multibit PE-PUF reduces the area usage around 30%. The proposed PE-PUF was fabricated and the experimental results confirm that the PE-PUF can operate reliably as low as 0.5 V, and hence, it is a remarkable candidate to be utilized in low-power applications. [ABSTRACT FROM AUTHOR]

Printed electronics is a fast-growing emerging technology, which is expected to play a major role in smart sensors for the Internet of Things domain. While there has been considerable progress at the device level by new materials, on circuit level results are still rare. In this letter, we report on the design, simulation, fabrication, and measurement of an inkjet-printed latch, which is an essential building block for digital circuits. Our technology approach is based on electrolyte-gated transistors, which enables low-voltage operation and yields an outstanding electrical performance due to high mobility of the semiconducting, precursor-made In2O3 channel. The fabricated latch can operate reliably down to 0.6 V, where the power consumption is only 16 \mu \textW . The area requirement is about 7 mm2, and in terms of lifetime, no performance degradation was observed during an experimental period of 12 weeks. [ABSTRACT FROM PUBLISHER]

Modern society is striving for digital connectivity that demands information security. As an emerging technology, printed electronics is a key enabler for novel device types with free form factors, customizability, and the potential for large-area fabrication while being seamlessly integrated into our everyday environment. At present, information security is mainly based on software algorithms that use pseudo random numbers. In this regard, hardware-intrinsic security primitives, such as physical unclonable functions, are very promising to provide inherent security features comparable to biometrical data. Device-specific, random intrinsic variations are exploited to generate unique secure identifiers. Here, we introduce a hybrid physical unclonable function, combining silicon and printed electronics technologies, based on metal oxide thin film devices. Our system exploits the inherent randomness of printed materials due to surface roughness, film morphology and the resulting electrical characteristics. The security primitive provides high intrinsic variation, is non-volatile, scalable and exhibits nearly ideal uniqueness. Designing efficient system for digital connectivity preserving information security remains a challenge. Here, the authors present hardware-intrinsic security solutions based on physical unclonable functions incorporating an inkjet-printed core circuit as an intrinsic source of entropy, integrated into a silicon-based CMOS system environment. [ABSTRACT FROM AUTHOR]

Electrolyte‐gated transistors (EGTs) represent an interesting alternative to conventional dielectric‐gating to reduce the required high supply voltage for printed electronic applications. Here, a type of ink‐jet printable ion‐gel is introduced and optimized to fabricate a chemically crosslinked ion‐gel by self‐assembled gelation, without additional crosslinking processes, e.g., UV‐curing. For the self‐assembled gelation, poly(vinyl alcohol) and poly(ethylene‐alt‐maleic anhydride) are used as the polymer backbone and chemical crosslinker, respectively, and 1‐ethyl‐3‐methylimidazolium trifluoromethanesulfonate ([EMIM][OTf]) is utilized as an ionic species to ensure ionic conductivity. The as‐synthesized ion‐gel exhibits an ionic conductivity of ≈5 mS cm−1 and an effective capacitance of 5.4 µF cm−2 at 1 Hz. The ion‐gel is successfully employed in EGTs with an indium oxide (In2O3) channel, which shows on/off‐ratios of up to 1.3 × 106 and a subthreshold swing of 80.62 mV dec−1. [ABSTRACT FROM AUTHOR]