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Quantum dots (QDs) can be used as conductive islands to build-up single-electron transistors (SETs). The characteristics of the QDs define the functional performance of the SETs. In consequence, analyzing the influence of the variations of QD dimensions on the performance of hybrid SET-FET circuits is of high relevance. We employ a self-developed SET compact model which is calibrated to 3-D quantum-mechanics-based simulations in order to obtain realistic model parameters. A method to improve the circuit behavior, i.e., to increase the output current, is proposed. It is concluded that the variation of the QD size presents the largest influence on the overall circuit behavior. [ABSTRACT FROM AUTHOR]

3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability. [ABSTRACT FROM AUTHOR]

Abstract: Hot-carrier degradation in pMOS transistors with Si1– x Ge x implantations in the source and drain areas is analyzed (SiGe S/D). A simulation methodology is developed to translate the effects to circuit simulators. This methodology is applied to study hot-carrier degradation in CMOS inverters designed with SiGe S/D pMOS transistors. The results show that although pMOS transistors with embedded SiGe S/D have a better device performance, these devices are more sensitive to hot-carrier degradation at both the device and circuit levels. [Copyright &y& Elsevier]

The degradation produced by channel hot-carrier (CHC) on short channel transistors with high-k dielectric has been analyzed. For short channel transistors (L<0.15 µm), the most damaging stress condition has been found to be VG=VD instead of the ‘classical’ VG=VD/2 determined for long channel transistors. In this work, experimentally validated simulations have been performed to demonstrate that this shift is not caused by the presence of the high-k layer but due to short channel effects. Furthermore, the CHC degradation lifetime has been evaluated, revealing larger operating voltages for high-k than for SiO2-based transistors. Copyright © 2010 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]