Search

Here we present a variation-aware design space analysis for threshold switch (TS) assisted memristive memory. TS is augmented in series with the standard one-transistor one-resistor (1T1R) cell structure of memristive memory, improving the read performance. The selective phase transitions in TS lead to an enhanced distinguishability between the stored data and lower power consumption during the read operation. Compared to the standard 1T1R cell, TS-augmented design achieves (for the nominal condition) 275% increase in read current ratio, 19% reduction in average read power, better read disturb margin, and 4% reduction in average write power at the cost of 75% increase in write ‘0’ delay and 50% increase in write energy. Here, we thoroughly explore the design space to show that the proper co-design of the components can further improve the proposed design. Our analyses will enable the proper choice of material and device parameters of the memristor and TS to utilize the full potential of the proposed design. We also explore the impacts of process variation through 10000-point $3\sigma$ Monte-Carlo analysis. [ABSTRACT FROM AUTHOR]

Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the scaling behavior of the system using simulations. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges. [ABSTRACT FROM AUTHOR]

We propose SRAMs and DRAM with independent read–write paths employing phase transition material (PTM) in the read port to enable a more compact design compared to standardmultiport cells. Our technique employs 1) the orders of magnitude difference in the resistances of the insulating and metallic phases of the PTM and 2) regulated phase transitions to design a 7T single-ended SRAM, an 8T differential SRAM, and a 2T DRAM. Compared to previously proposed 8T SRAM, our 7T design achieves 9.1% less cell area and our 8T design achieves differential read without area penalty. We extensively analyze the material requirements for PTM to enable the proposed cell operation. We show that the read performance of the proposed 7T cell is only 5% worse than previously proposed standard 8T, while the proposed 8T design shows a 38% improvement. Similarly, our 2TDRAM cell achieves 20% less cell area than 3T DRAM, with less than 6% read time penalty. The benefits for all the designs come at no write overheads. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viability of emerging memory technologies based on ferroelectric transistors (FEFETs) for our design. Compared to FEFET memory with standard 1-D access, we achieve 5% energy savings for the proposed memory featuring 2-D read and 93% energy savings for memory with 2-D read and write, for 32 bit column read and write. In addition, we get around 11% and 95% delay savings for 2-D read-enabled memory and 2-D read-write memory, respectively. The application analysis shows that 2-D read-enabled memory achieves around 86% average decrease in row-buffer transactions in $256\times 256$ size matrix operations without any array area increase. The 2-D read write memory offers 87% decrease in row-buffer transactions with 28.5% increase in array area compared to the 1-D FEFET memory. [ABSTRACT FROM AUTHOR]

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (B&R), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule B&R energy. This new nvDFF promises area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications. [ABSTRACT FROM AUTHOR]

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( T\textsf {FE}) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of T\textsf {FE} on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing T\textsf {FE} yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as T\textsf {FE} is increased. Depending on the attributes of the underlying transistor, increasing T\textsf {FE} beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of T\textsf {FE} on the circuit energy–delay. Our analysis shows that for high T\textsf {FE} , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay. [ABSTRACT FROM PUBLISHER]

We propose a novel static random access memory (SRAM) cell employing correlated material (CM) films in conjunction with the transistors to achieve higher read stability, write ability, and energy efficiency. The design of the proposed SRAM cell utilizes orders of magnitude difference in the resistance of the insulating and metallic phases of the CM to mitigate the design conflicts. By appropriately controlling the phase transitions in the CM films during SRAM operation through device–circuit codesign, we achieve 30% higher read static noise margin and 36% increase in the write margin over standard SRAM. The proposed design also leads to a 50% reduction in the leakage current due to high insulating state of the CM. This is achieved at 28% read time penalty. We also discuss the layout implications of our technique and present techniques to sustain no area overhead. [ABSTRACT FROM PUBLISHER]

We present a hybrid multiplexing (HYM) scheme for MRAMs with separate read-write paths, employing different bit-cell selection methods during read and write based on their suitability for data sensing and switching operations. The proposed technique allows the sharing of the read access transistor among the cells belonging to the same word, leading to area savings and enhancement in distinguishability. Furthermore, by employing dummy bits in an array and setting their values according to the process corner, the spread of the read current due to global variations can be tightened. We apply our technique on MRAM with spin Hall effect-based write and show that the HYM achieves 20% to 25% area reduction along with 2.4X improvement in cell TMR, 25% to 38% lower write power, and upto 50% increase in the read disturb margin compared to the standard multiplexing. The spread of the read current reduces by 38% to 53% by employing the dummy bits. [ABSTRACT FROM PUBLISHER]