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We present an investigation on the role of temperature and electric field as driving forces in the initiation of the resistive switching processes. The impact of temperature in both on- and off-states is analyzed in detail, using an electrothermal numerical model formulation. dc and pulsed temperature-dependent data, collected on scaled crossbar test structure cells, serially connected with an on-chip control transistor, are used to extract material information and are furthermore analyzed in conjunction with model outputs. With these results, further discussion is presented, suggesting points of attention for scaled cell design in the below-10-nm realm. [ABSTRACT FROM AUTHOR]

The endurance/retention performance of \HfO2/\break \Metal cap RRAM devices in a 1T1R configuration shows metal cap dependence. For Hf and Ti caps, owning strong thermodynamic ability of extracting oxygen from \HfO2, long pulse endurance (>\10^10 \ \cycles) could be achieved. For Ta cap, owning lower thermodynamic ability of extracting oxygen from \HfO2, better retention can be achieved. Therefore, an endurance/retention performance tradeoff is identified on the 40 nm \times 40 nm \HfO2/\Metal cap bipolar RRAM devices. The tradeoff of endurance/retention performance can be explained by a different filament constriction shape depending on metal cap layer as derived from fitting I– V curves in the quantum point contact model. This difference in filament constriction shape is attributed to the thermodynamics difference of metal cap: Hf and Ti have a stronger thermodynamical ability to extract oxygen from \HfO2 than Ta. The possibility of tuning the intrinsic reliability performance by changing the cap materials paves a way for optimizing the operation of RRAM devices into the desired specifics. [ABSTRACT FROM AUTHOR]

By tuning the SET/RESET pulse amplitude conditions, the pulse endurance of our 40-nm \HfO2\/Hf 1T1R resistive-random-access-memory devices demonstrates varying failure behaviors after \10^6\ \cycles. For unbalanced SET/RESET pulse amplitude conditions, both low-resistance state (LRS) and high-resistance state (HRS) failures may occur, while varying the pulsewidths influences the LRS/HRS window and the stability of the LRS/HRS states. The failure of the HRS or LRS state during cycling is ascribed to the depletion or excess of oxygen vacancies at the switching interface. Through a dc SET/RESET recovery operation, LRS/HRS states can be recovered after failure, indicating that the distribution of oxygen vacancies can be restored. By optimally balancing the SET/RESET pulse conditions, more than \10^10 pulse endurance cycles is achieved. [ABSTRACT FROM AUTHOR]