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We report the observation at low temperature of a hump in the linear transfer characteristic of a thin film fully depleted silicon-on-insulator transistor when a positive bias is applied on the back gate under the buried oxide. This decrease in the current is correlated with the transition from one-subband to two-subband conduction. Electron mobility measurements and calculations are in good agreement with the occurrence of intersubband scattering in carrier transport in the two-dimensional inversion layer. [ABSTRACT FROM AUTHOR]

The less surface roughness scattering effects, owing to the unique operation principle, in junctionless nanowire transistors (JLT-NW) were shown by low-temperature characterization and 2D numerical simulation results. This feature could allow a better current drive under a high gate bias. In addition, the dominant scattering mechanisms in JLT-NW, with both a short (LM = 30 nm) and a long channel (LM = 10 μm), were investigated through an in-depth study of the temperature dependence of transconductance (gm) behavior and compared to conventional inversion-mode nanowire transistors. [ABSTRACT FROM AUTHOR]

The mobility degradation by the relaxed electric-field in junctionless transistor (JLT) has been studied experimentally and theoretically. JLT showed less mobility degradation compared to the inversion-mode transistor in both planar-like and nanowire structures. The unique transconductance shape and the reduced degradation of the mobility in the nanowire JLT showed that it still has bulk neutral conduction portion in its total conduction while the immunity to the mobility degradation of JLT is enhanced with planar-structure. 2-dimensional numerical simulation confirmed the reduced transverse electric-field with bulk neutral conduction in JLT as well as the deviation of transconductance degradation by the channel doping concentration and the channel top width. [ABSTRACT FROM AUTHOR]

The error rate of low-field mobility (μ0) extracted from the conventional Y-function method in junctionless transistors (JLTs) is found to be linearly proportional to the channel doping concentration (Nd) for a typical value of the first order mobility attenuation factor θ0≈0.1V-1. Therefore, for a better understanding of their physical operation with higher accuracy, a methodology for the extraction of the low-field mobility of the surface accumulation channel (μ0_acc) and the bulk neutral channel mobility (μbulk) of JLTs is proposed based on their unique operation principle. Interestingly, it is found that the different temperature dependence between μ0_acc and μbulk is also confirming that the distribution of point defects along the channel in the heavily doped Si channel of JLTs was non-uniform. [ABSTRACT FROM AUTHOR]

This paper presents the low-temperature characteristics of flat-band (VFB) and low-field mobility in accumulation regime (µ0_acc) of n-type junctionless transistors (JLTs). To this end, split capacitance-to-voltage (C–V), dual gate coupling and low-temperature measurements were carried out to systematically investigate VFB. Additionally, the gate oxide capacitance per unit area Cox and the doping concentration ND were evaluated as well. Accounting for the position of VFB and the charge based analytical model of JLTs, bulk mobility (µB) and µ0_acc were separately extracted in volume and surface conduction regime, respectively. Finally, the role of neutral scattering defects was found the most limiting factor concerning the degradation of µB and µ0_acc with gate length in planar and tri-gate nanowire JLTs. [ABSTRACT FROM AUTHOR]

A wealth of convergent results are indicating that point defects originating from the processing of source/drain (S/D) regions are strongly involved in many parameters that rule the operation mechanisms and ultimately the performance of transistors. One example of such effect is the mobility degradation which is observed at short gate length in most, if not all, technologies. Defects can also been traced by their implication in leakage currents. Their dynamics has been found as well to be involved in the activation/deactivation processes and the final series resistance of S/D regions, enlightening the role of additional interfaces that are being introduced with thin film SOI and nanowire technologies. These complex effects, which are becoming 3D in present technologies, are very difficult to characterize by means of structural characterization. On the other hand, simulation based predictions have strongly improved. However, due to the complex processes involved, they still require the adjustment of a large number of parameters, which can usually be validated in model configurations only. In this paper we will review and complement some of our recent results obtained from electrical characterization, for a variety of advanced MOS transistor architectures, with focus on the analysis of the parameters which can be influenced by the presence of defects. It is shown that in-depth electrical characterization can provide strong experimental indications about point defects lateral distribution, with the advantage of probing the real device. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

A charge-based compact capacitance model has been developed describing the capacitance–voltage characteristics of undoped or lightly doped ultra-scaled triple-gate fin field-effect transistors. Based on a unified expression for the drain current and the inversion sheet charge density, i.e., the Ward–Dutton linear-charge-partition method and the drain current continuity principle, all trans-capacitances are analytically derived. The developed capacitance model is valid in all regions of operation, from the subthreshold region to the strong inversion region and from the linear region to the saturation region. The gate and source trans-capacitances have been validated by 3-D numerical simulations over a large range of device dimensions. The parameters of the capacitance model can be used to accurately predict the transfer and output characteristics of the transistors, making this compact model very useful for circuit designers. [ABSTRACT FROM AUTHOR]

We study the effect of surface roughness (SR) at the \Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson–Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors. [ABSTRACT FROM PUBLISHER]

This paper aims at reviewing the results that we have obtained during the last ten years in the characterization and modeling of transistor mismatch in advanced complementary metal–oxide–semiconductor (CMOS) technologies. First, we review the theoretical background and modeling approaches that are generally employed for analyzing and interpreting the mismatch results. Next, we present the experimental procedures and methodologies that we used for characterizing the transistor matching. Then, we discuss typical matching results that were obtained on modern CMOS technologies and analyze the main variability (mismatch) sources. Finally, we conclude by summarizing our findings and giving some recommendations for future technologies. [ABSTRACT FROM PUBLISHER]

This paper details the modeling of a one-transistor dynamic random-access memory (1TDRAM) based on an independent double-gate device. A pseudo-2-D compact model of memory operations and dynamic behavior of data retention is proposed. The physical mechanisms involved are calculated through the accumulated charge in the body modulated by quantum effects related to thin silicon films. The resulting currents from programming operations are detailed. We consider current leakages, generation/recombination, and band-to-band tunneling parasitic effects for data retention. [ABSTRACT FROM AUTHOR]

This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 μm bulk and silicon-on-insulator (SO!) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these technologies, and we compare small and long transistors electrical responses, evidencing the strong effect of source drain resistance Red. Then, using the same approach on short devices with different gate-edge-to-STI distances, we quantitatively evaluate stress profile induced by STI and its mean value under the gate of the devices. Results are discussed to explain differences between bulk and SOI technologies, as well as between nMOS and pMOS. We show that the observed higher pMOS drain current shift is related to the process, and may be explained by doping amorphization and recrystallization effects, and not by a piezoresistive coefficient difference as usually assumed. [ABSTRACT FROM AUTHOR]

This letter demonstrates a new technique to extract the source/drain series resistance of MOSFETs. Unlike the well-known total resistance techniques, Rsd is extracted in a way that the result is insensitive to effective length and mobility variations. The technique has been successfully applied to 45-nm bulk and fully depleted SO! MOSFETs with high-k and metal gate, having channel length down to 22 nm. The technique provides a high accuracy and allows fast measurements and statistical analysis. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we study the bipolar transistor characteristic matching in all current ranges. At low current, the phenomena responsible of the base current mismatch degradation are interpreted and a new base current mismatch model is derived. At medium current, the physical origins of the mismatch in bipolar transistors are investigated leading to new mismatch models. Moreover, matching performances of Si/SiGe(:C) heterojunction bipolar transistors, processed in several BiCMOS technologies, are characterized and compared. In the high current region, the impact of the emitter resistance mismatch on the base and the collector current mismatch degradations is fully demonstrated. [Copyright &y& Elsevier]

In this work, the effect of high channel doping concentration and unique structure of junctionless transistors (JLTs) is investigated in the subthreshold conduction regime. Both experimental results and simulation work show that JLTs have reduced portion of the diffusion conduction and lower effective barrier height between source/drain and the silicon channel in subthreshold regime, compared to conventional inversion-mode (IM) transistors. Finally, it leads to a relatively large DIBL value in JLTs, owing to degraded gate controllability on channel region and strong drain bias effect. However, JLTs showed a better immunity against short channel effect in terms of degradation of the effective barrier height value. [ABSTRACT FROM AUTHOR]

Highlights: [•] The back bias effect on junctionless transistors (JLTs) has been investigated. [•] JLTs are more sensitive to back biasing compared to inversion-mode device. [•] The effective mobility of JLT is enhanced below flat band voltage by back bias. [•] The back bias effect in narrow JLTs is suppressed. [•] 2-D numerical simulation successfully reconstruct of the trend of back bias effects. [Copyright &y& Elsevier]

Highlights: [•] Impact of Ge content on Vt, β, and Id mismatches in advanced PMOSFETs. [•] Global improvement ofelectrical parameters mismatchobserved in PMOSETs with SiGe channel. [•] The reduction of Coulomb scatteringwith the introduction of Ge improves β mismatch. [Copyright &y& Elsevier]

Abstract: The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (W top_eff) was investigated, experimentally. As decreasing W top_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (C gc–Vg ), resulting in a noticeable change in the effective mobility (μ eff) behavior from that in wide JLT devices, an increase of the threshold voltage (V th), while the flat-band voltage (V fb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure. [Copyright &y& Elsevier]

Abstract: In this work, the drain-current mismatch is characterized from linear to the saturation regime. Characterizations are performed for N-MOS transistors with and without pocket-implants. A general drain-current mismatch model for transistors without pocket-implants, valid for any operation region, is also presented. It has been shown that correlated mobility and threshold voltage fluctuations must be considered to qualitatively model the experimental results. A comparison between devices with and without pocket-implants is performed and an important drain-current mismatch enhancement in the latter case is reported and discussed. [Copyright &y& Elsevier]

• Back bias offers a unique way to optimize devices operating at low temperature. • Forward back biasing allows reducing the power consumption. • Electrostatics can be successfully modelled by 1D PS calculation down to 4.2 K. • Short channel devices suffer from stronger T-independent scattering mechanisms. • Cryogenic operation enhances the cut-off frequency due to improvements in transport. 28 nm FD-SOI technology is electrically characterized aiming at cryogenic applications. Electrostatics and transport are evaluated and compared while lowering temperature from 300 K down to 4.2 K. Split CV technique is applied in both long and short channel transistors thanks to multiple parallel structures designed to increase the gate area. FD-SOI versatility is shown over a wide temperature range of operation, as the back gate tuning efficiency is preserved at low temperatures. Insights on back gate bias behavior at room and low temperatures are obtained and the electrostatic coupling between front and back channels can be successfully modelled by using 1D Poisson-Schrödinger calculation from 300 K down to 4.2 K. A generic form of empirical models for the effective mobility is found to be useful for cryogenic operation, since the phonon scattering contribution presents strong temperature dependence. While long channel MOSFETs exhibit strong mobility improvement, short channel transistors show lower mobility gain with temperature reduction. [ABSTRACT FROM AUTHOR]

Abstract: For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on Gate-All-Around transistors (GAA) with both doped and undoped channels. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants. But most of all, it is shown that suppressing the channel doping allows to drastically reduce the dopant induced fluctuations contribution and provides an parameter as low as 1.4mVμm, which is one of the best reported result on MOS transistors. [Copyright &y& Elsevier]

• Subthreshold operation of tri-gate junctionless transistors (JLTs) with various effective width (W eff) was investigated. • Physical operation mechanism on the subthreshold regime of JLTs was also discussed in detail. • The on current to off current ratio (I on /I off) and subthreshold swing (SS) of JLTs were varied dramatically as changing W eff. • Remained carriers at the bottom caused a higher off-current, a deviated shape of log 10 (n) derivatives. • In addition, a better immunity against short channel effects (SCEs) in JLTs was proven. Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (W eff) and compared to that of IM transistors. The on current to off current ratio (I on /I off) and subthreshold swing (SS) of JLTs were varied dramatically as changing W eff. In addition, a better immunity against short channel effects (SCEs) of JLTs was proven. Physical operation mechanism on the subthreshold regime was also discussed in detail with considering distribution of mobile charge carriers, maximum depletion width, full-depletion mode, bulk neutral and surface accumulation conduction. [ABSTRACT FROM AUTHOR]