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We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ($I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{\text {1-x}}\text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer (${A}_{Fe}$) and the metal–oxide–semiconductor layer (${A}_{MOS}$), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~\mu \text{A}/ \mu \text{m}$ (${V}_{\mathrm{GS}} - {V}_{\mathrm{TH}}$ = 5 V and ${V}_{\mathrm{DS}}$ = 2 V) and ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V. [ABSTRACT FROM AUTHOR]

To enable heterogeneous integration of InGaAs based transistors with Si complementary metal-oxide-semiconductor (CMOS) devices, metal contacts to n+-InGaAs need to have high thermal stability for CMOS process compatibility and ultra-low contact resistance to achieve good device performance. In this work, n+-InGaAs contacts with ultra-low contact resistivity pc based on refractory metals such as molybdenum (Mo) were realized. Use of refractory metal contacts achieves good thermal stability. An improved process that eliminates oxide between the metal and n+-InGaAs by using an in situ Ar+-plasma treatment prior to metal deposition achieves ultra-low pc. Furthermore, a nano-scale transmission line method (nano-TLM) structure with significantly reduced parasitic leakage was designed and fabricated to improve the pc extraction accuracy. The improved test structure introduces a SiO2 isolation layer between Mo and InGaAs outside the active or mesa region to eliminate a parallel leakage path that is present in other nano-TLM structures reported in the literature. [ABSTRACT FROM AUTHOR]

We report the temperature-dependent operation of back-end-of-line (BEOL) compatible amorphous indium-gallium-zinc-oxide (${a}$ -IGZO) ferroelectric thin-film transistors (FeTFTs) with a large memory window (MW) more than 3 V. Our ${a}$ -IGZO FeTFTs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) stru- cture with Zr-doped HfO2 (HZO) as the ferroelectric layer. Characteristics of ${a}$ -IGZO FeTFTs are investigated in the temperature range of −40 °C to 100 °C. We found that: Firstly, the remanent polarization (${P}_{\text {r}}$) of the HZO film increases with $2{P}_{\text {r}}$ from $\sim 35~ {\mu }\text{C}$ /cm2 at −40 °C to $\sim 40~ {\mu }\text{C}$ /cm2 at 100 °C. Secondly, enhancement in MWs at high temperatures is observed, achieving MWs larger than 3.5 V when the temperature is higher than 60 °C. Thirdly, for the threshold voltage (${V}_{\text {TH}}$) at high temperatures, there is a competition between the negative shift caused by higher carrier concentration in the ${a}$ -IGZO channel and positive shift due to the charge trapping at the floating gate in the MFMIS structure. This could be explored to realize good ${V}_{\text {TH}}$ stability. [ABSTRACT FROM AUTHOR]

We investigate the effect of channel layer thickness on effective mobility (μeff) in the sub-10-nm regime of amorphous indium–gallium–zinc–oxide thin-film transistors (α-IGZO TFTs). TFT devices with extremely scaled channel thickness tα-IGZO of 3.6 nm were realized, exhibiting low subthreshold swing (SS) of 74.4 mV/decade and the highest effective mobility μeff of 34 cm2/V ⋅ s at a carrier density NCarrier of ~ 5 × 1012 cm−2 for any kind of α-IGZO TFTs having sub-10-nm tα-IGZO. No significant degradation of μeff is observed as α-IGZO thickness reduced from 6 to 3.6 nm. By scaling down the channel length LCH to 38 nm, high extrinsic transconductance (Gm, max) of 125 μs/μm (at VDS of 1 V) and ON-state current ION of 350 μA/μm at VGS – VT of 3 V with VDS of 2.5 V are achieved. [ABSTRACT FROM AUTHOR]

We report high performance amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transis- tors (TFTs) with 10 nm atomic-layer-deposited HfO2 as the gate dielectric, achieving subthreshold swing (SS) of 70.2 mV/decade, high effective mobility (μeff) of 55.3cm2/V⋅s at an inversion carrier density (Ninv) of 5 × 1012 cm−2, and large ION/IOFF of > 109. Furthermore, very good device-to-device uniformity has been confirmed by the statistical distribution of SS and maximum transconductance (Gm, max) measured from 20 pristine TFT devices. This a-IGZO TFT has immense potential for the ultrafast and low power electronic devices for next-generation cost-effective emissive display, image sensing, and hardware for artificial intelligence (AI). [ABSTRACT FROM AUTHOR]

Germanium–tin (GeSn) p-channel fin field-effect transistor (p-FinFET) was realized on a novel GeSn-on-insulator (GeSnOI) substrate. The high-quality GeSnOI substrate was formed using direct wafer bonding technique and was layer-transferred from a 300-mm GeSn/Ge/Si donor wafer. Material quality was examined using atomic force microscopy, high-resolution transmission electron microscopy, Raman spectroscopy, and high-resolution X-ray diffraction. The fabricated GeSn p-FinFETs exhibit a small subthreshold swing (${S}$) of 79 mV/decade at ${V}_{\text {DS}}$ of −0.05 V (by a device with ${L}_{\text {CH}}$ of 200 nm and ${W}_{\text {Fin}}$ of 30 nm), good control of short channel effects, and high intrinsic transconductance (${G}_{m,\text {int}} = 702\,\,\mu \text {S}/\mu \text{m}$ at ${V}_{\text {DS}}$ of −0.5 V for ${L}_{\text {CH}}$ of 80 nm). Low-temperature mobility analysis was performed on the GeSn p-FinFETs. High effective hole mobility ($\mu _{\text {eff}}$) (210 cm2/ $\text {V}\cdot \text {s}$ at 290 K and 398 cm2/ $\text {V}\cdot \text {s}$ at 5 K) is achieved. The GeSn p-FinFETs presented in this paper exhibit the highest ${G}_{m,\text {int}}/{S}_{\text {sat}}$ at ${V}_{\text {DS}}$ of −0.5 V for all the reported GeSn p-FETs to date. [ABSTRACT FROM AUTHOR]