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To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat. [ABSTRACT FROM AUTHOR]

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LETth) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V. [ABSTRACT FROM AUTHOR]

The single event upset (SEU) for monolithic 3-D (M3D) 6T SRAM with different channel sizes was investigated based on a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology over a temperature range from 210 K to 390 K. Compared with planar SRAM, M3D SRAM exhibits higher SEU sensitivity and increasing the transistor size does not work in mitigating the SEU in M3D. It is also demonstrated that the SEU sensitivity of M3D 6T SRAM enhances with temperature rising after the incident of 127I while it decreases after the striking of 209Bi. The reason can primarily be explained by the different influence ranges of striking heavy ions, which affect the ionized charge transport. [ABSTRACT FROM AUTHOR]