Search

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) $ZrO_{2}$ based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ($t_{FE}$ and $t_{IL}$ , respectively) on device performance. We observe that a decrease of $t_{FE}$ and $t_{IL}$ reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of $t_{FE}$ , $t_{IL}$ and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood. [ABSTRACT FROM AUTHOR]

A ferroelectric material in a ferroelectric–dielectric heterostructure can provide a charge boost, as often discussed in the context of negative capacitance, and, in doing so, can reduce the power dissipation in field-effect transistor technology. However, there is an ongoing debate on whether the charge boost in such a heterostructure is a transient phenomenon or a steady state one. In this Letter, we use the positive-up-negative-down (PUND) measurement technique on a ferroelectric–dielectric (FE–DE) capacitor to show that the charge boost is a steady-state effect—i.e., the charge boost remains intact after the initial transient effects subside and all the voltages in the system reach constant values and steady states. We also demonstrate differential charge boost in steady state using a staircase voltage pulse measurement technique. An experimentally calibrated multi-domain SPICE model of an FE–DE stack is used to accurately simulate the PUND and staircase voltage hopping methods. [ABSTRACT FROM AUTHOR]