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In this letter, a voltage reference circuit based on amorphous InGaZnO-based (a-IGZO) thin-film transistors (TFTs) is reported for the first time. Both enhancement-mode and depletion-mode TFTs in the circuit were fabricated by the use of local hydrogen doping. The 1-V reference voltage ($\text{V}_{\text {REF}}$) was achieved with an operating voltage ranging from 1.2 V to 5 V, where the line sensitivity of $\text{V}_{\text {REF}}$ was 0.9%/V and the quiescent consumption was as low as 90 nW. The proposed voltage reference circuit was able to generate complementary- to-absolute temperature coefficients, resulting in stable temperature characteristics. The temperature coefficient (TC) of $\text{V}_{\text {REF}}$ and $\text{I}_{\text {REF}}$ was studied experimentally, where the TC of $\text{V}_{\text {REF}}$ was 2.3 mV/° at a temperature spanning from 27 ° to 77 °. [ABSTRACT FROM AUTHOR]

In this paper, a single particle irradiation experiment is performed on the 600 V trench insulated gate bipolar transistor for the first time. The experimental results show that, at the collector voltages of 100 V and 300 V, single event gate rupture occurs in the device under the linear energy transfer of 81.35 MeV cm2/g. The damage occurs in the gate oxide layer near the bottom of the trench gate. The simulation results show that the holes accumulated at the bottom of the trench gate increase the electric field under irradiation, which causes the failure of the gate oxide. Furthermore, the hardening device structure is proposed by increasing the thickness of the bottom gate oxide. [ABSTRACT FROM AUTHOR]

Because of the extremely narrow dc thermal safe operating area for 700-V high-voltage lateral double-diffused MOS (LDMOS) transistor, the gate duty-cycle-accelerated ac stress was adopted to investigate its hot-carrier-induced degradations. It is found that there are different degradation mechanisms with different amplitudes of ac gate stress, including the maximum operating gate voltage (Vgmax) stress and the maximum substrate current (Isubmax) stress. For the Vgmax condition, the ON-resistance (RON) decreases first and increases finally, which is attributed to two competitive degradation mechanisms. One is the hot holes injection at the bird’s beak during the gate pulse edges, and the other one is the hot electrons injection nearby the drain during the high state level of gate pulse. However, for the Isubmax stress, the dramatical injection of hot electrons nearby the source-metal edge during the high state level of gate pulse is always the main degradation mechanism, resulting in a monotonous increase of RON. Moreover, the threshold voltage (Vth) degradations could be neglected due to the intact channel region under the Vgmax and Isubmax conditions. In this way, the Isubmax condition is regarded as the worst stress, and an improved device with a linear-doped buried-p-well (BP) structure beneath the P-body has been proposed to restrain the degradation under the worst stress condition. [ABSTRACT FROM AUTHOR]

In this paper, the degradation mechanisms of the bottom-gate amorphous InGaZnO thin film transistors (a-IGZO TFTs) under positive gate bias stress (PBS) are investigated. The PBS-induced degradation can be attributed to the electron capture at the interface of the gate insulator and a-IGZO and the generation of oxygen interstitial defects (O i) in a-IGZO. The oxygen interstitial defect density (N Oi) can be calculated by the degradation of SS during recovery after PBS. It is found that the proportion of degradation caused by O i increases with the increased a-IGZO thickness. By utilizing NH 3 plasma treatment, the threshold voltage shift was reduced by >40 % under PBS (@V G = 5 V, t = 1000s). Further analysis shows that NH 3 plasma treatment can effectively suppress the electron capture at the interface and the generation of O i during PBS. Thus, PBS reliability of a-IGZO TFTs is improved by the proposed method. • The degradation mechanisms of the a-IGZO TFTs under PBS are investigated. • The electron capture and the generation of O i caused PBS-induced degradation. • The proportion of degradation caused by O i increases with the increased a-IGZO thickness. • PBS reliability of a-IGZO TFTs can be improved by utilizing NH 3 plasma treatment. [ABSTRACT FROM AUTHOR]

We demonstrate an experimental study on the ballistic transport behavior of sub-100 nm GeOI n-MOSFETs, by adopting an ultrafast pulsed I–V system for measurement. High performance GeOI n-MOSFETs suffer severer self-heating effect and traps in the dc characterization process than in a “real” high-speed IC circuit. In this letter, the ballistic transport parameters for nanoscale Ge n-MOSFETs are extracted by the pulsed I–V method, and is compared with the SOI n-MOSFETs. The ballsiticity for Ge MOSFETs is higher than Si transistors at the same gate length L\text {G} . Furthermore, the scalability of the ballistic parameters for Ge n-MOSFETs is modeled and predicted for the sub-10-nm technology nodes. [ABSTRACT FROM PUBLISHER]

Alloy scattering in a sSi/Si0.5Ge0.5/strained Silicon on Insulator (SOI) (sSOI) quantum-well (QW) p-MOSFET is investigated by hole density modulation through applying back-gate biases. The hole mobility under negative back-gate biases is found degraded by intensified alloy scattering at low electrical field because more holes are distributed in the bulk Si0.5Ge0.5. At higher electrical field, the higher density of holes populated at the Si/Si0.5Ge0.5.interface and less holes in the bulk Si0.5Ge0.5.result in less pronounced alloy scattering, leading to mobility enhancement under negative back-gate biases. This confirms experimentally that alloy scattering does not play a significant role in the hole mobility of sSi/Si0.5Ge0.5/sSOI QW p-MOSFETs under normal operating mode. [ABSTRACT FROM PUBLISHER]