1. Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO$_{{x}}$ /Si Substrates Using Area-Selective CVD Technology
- Author
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Chao-Ting Lin, Kai-Shin Li, Wen-Bin Jian, Chao-Ching Cheng, Sheng-Kai Su, Chao-Hsin Chien, Jyun-Hong Chen, Lain-Jong Li, Tung-Yen Lai, Chen Tzu-Chiang, Ming-Yang Li, Chiang Hung-Li, Jia-Min Shieh, Chi-Feng Li, H.-S. Philip Wong, Kuan-Cheng Lu, and Yun-Yan Chung
- Subjects
010302 applied physics ,Materials science ,Silicon ,business.industry ,Tungsten disulfide ,chemistry.chemical_element ,Tungsten ,01 natural sciences ,Exfoliation joint ,Electronic, Optical and Magnetic Materials ,chemistry.chemical_compound ,chemistry ,Transmission electron microscopy ,0103 physical sciences ,MOSFET ,Optoelectronics ,Dry transfer ,Electrical and Electronic Engineering ,business ,Deposition (law) - Abstract
For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiO x /Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 106, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
- Published
- 2019