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In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts. [ABSTRACT FROM AUTHOR]

• A network flow model of the VLSI processor array is constructed under row and column rerouting. • A new strategy for selecting the bottleneck row in the logic array using the minimum cutting technique is proposed. • The proposed schemes significantly reduce the interconnect redundancy of the logical subarray. The reconfiguration algorithms have been extensively investigated to ensure the reliability and stability for the processor arrays with faults. It is important to reduce the power consumption, capacitance and communication costs in the processors by reducing the interconnection length of the VLSI array. This paper discusses the reconfiguration problem of the high-performance VLSI processor array under the row and column rerouting constraints. A novel method, making use the idea of network flow, is proposed in this paper. Firstly, a network flow model of the VLSI processor array is constructed, such that the high-performance VLSI target array can be obtained by utilizing the minimal cost flow algorithm. Secondly, we propose a new strategy for bottleneck row selection in the logical array using the minimum cut technique, which can find a more suitable bottleneck row. Finally, we conducted reliable experiments to clearly reveal the efficiency of the new rerouting scheme and algorithm in reducing the number of long interconnects. The experimental results show that, for a host array with size of 256×256, the number of long interconnects in the subarray can be reduced by up to 79.22% and 55.88% without performance penalty for random faults with density of 1% and 25% respectively, when compared with state-of-the-art. In addition, the proposed scheme improves existing algorithm in terms of subarray size. On a 256×256 host array with 25% faulty density, the average improvement in subarray size is up to 3.77% compared with state-of-the-art. [ABSTRACT FROM AUTHOR]

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound. • A mathematical model for VLSI array reconstruction is established. • The interconnection of the array is set to a function with a fixed integer variable. • The problem is transformed into solving the objective function. • A novel method was proposed constructing tightly coupled sub-arrays. [ABSTRACT FROM AUTHOR]

Reducing the number of visits to failure-free nodes can effectively reduce the reconstruction time of logical columns and improve the reconstruction efficiency. In this paper, we describe a new method to speed up the reconfiguration for the VLSI arrays. An efficient algorithm was proposed based on shortest path first principle for accelerating reconfiguration of VLSI processor subarrays with high power efficiency to meet the requirement of the power consumption of embedded system. The proposed algorithm greatly reduces the number of visits to the fault-free PEs for constructing a local optimal logical column and effectively reduces the construction time. Experimental results show that the proposed algorithm is capable of reducing the consumption time by 32.15% and reducing the numbers of visited PEs by 49.61% for a 128 × 128 host array with 20% falut rate. • We propose an algorithm based on shortest-path-first, which effectively reduce the number of visited PEs. • We prove that the time complexity of the algorithm is lower than that of previous algorithms. • We show that the scheme effectively reduces the time of reconfiguration and get the subarray in polynomial time. [ABSTRACT FROM AUTHOR]

In the mesh-connected processors, some processor elements (PEs) become ineffective due to high temperature, overload and other factors, which can affect the stability of the system. This paper deals with the problem of reconfiguring the largest possible subarray from the processor with faults under the row and column rerouting constraint. Firstly, a flexible routing scheme, based on dynamic programming, is proposed to construct the local optimal logical columns. Secondly, we discuss and revise the PEs that cannot be connected between every two logical columns under this scheme. Finally, an efficient algorithm is presented to construct the maximum subarray in polynomial time. The experimental results show that, both on the random and clustered fault scenarios, the proposed algorithm under flexible rerouting scheme is capable of constructing the larger scale logical arrays. On a 48 × 48 host array with 15% fault density, the improvement on the use of fault-free PEs is up to 6.22% for random faults. On a 256 × 256 host array, the improvement can be up to 85.60% for clustered faults. Moreover, the proposed algorithm runs faster than previous algorithms under different size arrays and fault densities, the average improvement in running time is up to 99% compared with state-of-the-art. • A dynamic programming method is used to construct the logical columns. • An efficient heuristic algorithm is proposed to construct larger subarrays. • The proposed scheme and algorithm effectively reduce the running time. [ABSTRACT FROM AUTHOR]

Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage of the previous network model and the low-performing of standard network flow algorithms for reconfiguration, the efficiency of these algorithms is poor for constructing the high performance VLSI subarray. In this paper, we present an efficient multiple shortest augmenting paths algorithm for rapidly constructing high performance VLSI array. Firstly, we proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm. Secondly, a multiple shortest augmenting path algorithm based on the new data structure is proposed, which can significant reduce the running time. Finally, we conduct solid experiments to highlight the efficiency of the proposed method in terms of the running time compared to the standard network flow algorithms. The experimental results show that on a 64 × 64 host array with 0.1% faults, the size of the network model can be reduced by about 50% and the average improvements in running time is up to 85.10% compared with four standard network flow algorithms. • An efficient data structure is proposed to decrease the size of the model to half the original model. • We develop a multiple shortest augmenting path algorithm to find multiple shortest paths at one time. • We prove that the proposed scheme can effectively reduce the running time of the reconfiguration in polynomial time. [ABSTRACT FROM AUTHOR]