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This paper postulates a tunable active inductor-based voltage controlled oscillator for IEEE 802.11 a/b/g/n/ac applications in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor which uses regulated cascode is implemented along with tuning competency. The layout-based simulation has been performed considering parasitic resistances and capacitances. The designed VCO yields an oscillation frequency ranging from 1.93 GHz to 5.97 GHz having tuning scope of 102%, where the tuning voltages is varied from 0 V to 0.8 V. The power consumption varies from 0.97 mW to 3.32 mW, and the VCO provides a differential output power of 3.29 dBm to −4.76 dBm. The phase noise varies from −78.52 dBc/Hz to −70.45 dBc/Hz, and the figure of merit (FOM) has a value of −143.63 dBc/Hz @ 5.09 GHz frequency. The designed VCO has been passed through process corner analysis, Monte Carlo analysis, stability analysis and temperature swept analysis to evaluate its compatibility. Furthermore, the elimination of MOS varactor has reduced overall silicon area consumption (39.73 × 25.3 \mum). Finally, the designed VCO's performance parameters have been compared with referred designs where it is illustrated that the designed VCO outperforms the others in most cases along with a good scope for implementing both 2.4 GHz and 5 GHz frequency that is, IEEE 802.11a/b/g/n/ac applications. [ABSTRACT FROM AUTHOR]

This paper presents a wideband varactorless voltage controlled oscillator (VCO) based on tunable active inductor in 90 nm CMOS process which yields a tuning range of 1.22 GHz to 3.7 GHz having a tuning scope of 100.5%. The designed VCO can be used for wideband wireless applications. The proposed VCO consumes a very low power (1.05~2.5) mW with the change of tuning voltages (0.3~0.9) V and provides a differential output power of (1.17~-5.13) dBm. The VCO exhibits phase noise of -80.50 dBc/Hz @ 2.74 GHz and the Figure of merit (FOM) is -147.73 dBc/Hz @ 2.74 GHz at 1MHz offset frequency. Achievement of high tuning range by altering the inductance of inductor which paves the way for eliminating the MOS varactor that recedes the overall silicon area consumption, is the noteworthy outcome of the proposed VCO. Furthermore, considering the dc power consumption, Figure of merit (FOM) and consistency of performance parameters over tuning range, the proposed VCO outstrips the other referred VCOs. [ABSTRACT FROM AUTHOR]

This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90 nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46 GHz for the tuning voltage of 0.3–1.5 V. It consumes a low dc power ranging from 2.44 mW to 4.79 mW for the specified tuning range. The variation of phase noise ranges from − 8 3. 0 3 dBc/Hz to − 7 8. 6 5 dBc/Hz at 1 MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of − 1 4 8. 8 5 dBc/Hz with a differential output power of 1.8 dBm at tuning voltage of 0.7 V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs. [ABSTRACT FROM AUTHOR]

This paper presents a tunable active inductor based ultra-low power, low area voltage-controlled oscillator (VCO) in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor is employed along with tuning capability. The layoutbased simulation has been performed deeming parasitic resistances and capacitances. The designed VCO yields an oscillation frequency ranging from 1.38 GHz to 3.16 GHz with a tuning range of 78.41%, where the tuning voltage is driven from 0.4 V to −0.2 V. The power dissipation varies from 0.062 mW to 0.177 mW, and the VCO provides a differential output power of 8.34 dBm to 3.94 dBm. The phase noise varies from −71 dBc/Hz to −65.4 dBc/Hz, and the Figure of Merit (FoM) has a value of −143.09 dBc/Hz @ 2.79 GHz frequency. The process corner analysis, temperature swept analysis, and Monte Carlo analysis of the proposed VCO had been carried out for the evaluation of its compatibility for diversified environments. Furthermore, the exclusion of the MOS varactor has condensed total silicon area consumption (10.3 μm × 8.5 μm). Finally, the designed VCO's performance parameters have been compared with mentioned designs where it is demonstrated that the designed VCO outdoes the others in most cases along with outstanding outcomes of low power and low silicon area consumption. [ABSTRACT FROM AUTHOR]

This Letter describes a current-reuse class-B/C hybrid voltage-controlled oscillator (VCO) with robust startup, enhanced phase noise and differential balancing at small area and power. Specifically, an asymmetrical CMOS class-C core is aided by a symmetrical NMOS-only class-B core that effectively shares the bias current for deeper class-C operation of the former; wider margin of startup against PVT variations, and lower amplitude imbalance against oscillation frequencies. Moreover, this topology adds the freedom of adjustable peak dynamic current and boosts the oscillation swing at low power. The spiral inductors with patterned ground shields shrink the die size. Fabricated in 65 nm CMOS, the 0.07 mm^2 VCO prototype exhibits 10.15-to-11.17 GHz tunability, and -107.73-dBc/Hz phase noise at 1 MHz offset, while dissipating merely 2.2 mW at 1.2 V. The achieved area-included figure-of-merit (FoMA = 196 dBc/Hz) favorably compares with the state-of-the-art. [ABSTRACT FROM PUBLISHER]

A compact realization of hybrid class-B/C quadrature voltage-controlled oscillator (QVCO) with output buffering is proposed. It employs a four-phase amplitude detector feedback loop to shift the operation mode from hybrid class-B/class-C to class-C after power up. The power-efficient class-C core allows quadrature-locking via passive capacitive coupling, whereas the auxiliary class-B core ensures a robust startup. For higher output drivability, PMOS-based source followers are stacked atop the QVCO for reusing its bias current and avoiding any AC-coupling networks. The buffered QVCO can directly drive up the 50-\Omega port of testers, or to withstand a large capacitive load in on-chip signal distribution. The fabricated 9 GHz QVCO in 65 nm CMOS draws 10.5 mW and exhibits -99.37-dBc/Hz phase noise at 1 MHz offset. The active area is just 0.137 mm^2 by using two compact spiral inductors with patterned ground shields. [ABSTRACT FROM PUBLISHER]