Search

This article compares the dual active bridge (DAB) and LLC converter topologies when utilized in a high-step-down fixed-conversion-ratio application, such as the dc–dc stage in laptop and LED TV adapters. Multiple candidate topologies for this application are compared, motivating the selection of the DAB and the LLC for further investigation. The two converters are first compared using first-order insights, and then using a detailed analytical design methodology focused on zero-voltage switching. Fundamental tradeoffs between conduction and switching losses are analyzed, predicting that the DAB converter should achieve higher efficiency at heavy loads due to lower conduction losses, while the LLC converter should achieve higher efficiency at lighter loads due to lower switching losses. To validate these predictions, design examples are developed for a 1-MHz 400–20 V 330-W application, and experimental prototypes for both converters are built based on these designs. Measured results match well with the predictions. The DAB prototype achieves a peak efficiency of 94.9% at full load, corresponding to a 27% reduction in losses compared to the LLC prototype. [ABSTRACT FROM AUTHOR]

The Class Φ2/EF2 amplifier is an attractive topology for high-voltage and high-frequency power conversion because of the high efficiency, reduced device voltage stress, simplicity of gate driving, and load-independent ZVS operation. Due to many degrees of freedom for tuning, previous studies can only solve the single-ended Φ2 circuit using numerical methods. This work focuses on improving the design and operating characteristics of a push–pull Φ2 amplifier with a T network connected between the switch nodes, or a PPT Φ2 amplifier. The PPT Φ2 amplifier has less circulating energy and achieves higher cutoff frequency ƒT than other Φ2/EF2 circuits. We, then, present a series-stacked input configuration to reduce the switch voltage stress and improve the efficiency and power density. A compact 6.78-MHz, 100-V, 300-W prototype converter is demonstrated that uses low-cost Si devices and achieves 96% peak total efficiency and maintains above 94.5% drain efficiency across a wide range of voltage and power. Together with the advances in wide-bandgap semiconductors and magnetic materials, the PPT Φ2 circuit opens more possibilities for the state-of-the-art performance of solid-state RF amplifiers in high-frequency, high-power applications, including wireless charging for electric vehicles, plasma RF drives, and nuclear magnetic resonance spectroscopy. [ABSTRACT FROM AUTHOR]

High step-down dc/dc converters are widely utilized in telecom and modern industrial applications. Due to the high step-down ratio, conventional Buck converter cannot provide satisfactory performance. To solve this problem, quite a few new topologies have been proposed to improve the performance of high step-down dc/dc converters, such as series-capacitor Buck (SC-Buck) converter, 3-level Buck converters, tapped inductor Buck converters, and LLC resonant converters. In this paper, the twice step-down benefit of SC-Buck converter and the zero-voltage switching benefit of series-capacitor tapped Buck (SC-TaB) converter are combined together to propose a new topology: interleaved series-capacitor tapped Buck (ISC-TaB) converter. To analyze the performance of the proposed ISC-TaB converter, the operation principles are discussed and the voltage conversion ratio is derived. In addition, to guide the design procedure and optimization, the current waveforms and voltage waveforms of the proposed ISC-TaB are derived. In order to verify the performance of the proposed ISC-TaB, hardware prototype of the proposed ISC-TaB converter and conventional two-phase series-capacitor tapped Buck converter (2ph-TaB) are designed and tested. The application is targeted at telecom with 48-V input and 3.3 V/20 A output. The test results are compared between these two converters. A peak efficiency of 95.6% is achieved on the proposed ISC-TaB and the efficiency of the ISC-TaB over all load range is at least 1% higher than that of 2ph-TaB. [ABSTRACT FROM AUTHOR]

Single-phase universal-input ac–dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz–4 MHz) across universal input voltage range (85  $\rm V_{\text{ac}}$ –265  $\rm V_{\text{ac}}$). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12  $\rm V_{\text{dc}}$ output, isolated multitrack PFC system with a power density of 50 W/in $^3$ , and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture. [ABSTRACT FROM AUTHOR]