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The current‐limiting reactor is currently the most used fault current limiting technique to ensure the fault ride‐through of the multi‐terminal dc grid. However, its configuration will significantly prolong the fault current clearance time and increase the dissipated energy of dc circuit breakers. Therefore, this paper proposes a cost‐effective multiline fault current limiter for multiport application in multi‐terminal dc grids, which can effectively limit the rising speed of fault current through the integrated current‐limiting reactors without time delay and significantly reduce their negative impacts on the performance of dc circuit breakers by bypassing the current‐limiting reactors through the solid‐state switch units during the fault current interruption process. The topology and operation process of the multiline fault current limiter are introduced at first. Then, the economic comparison of the proposed device with the existing solutions is presented. Finally, the feasibility and superiorities of the proposed device are verified by extensive simulations and scaled‐down experiments. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

During the low‐voltage ride‐through (LVRT) of the doubly fed induction generator (DFIG), the change rate of the stator flux is introduced as the feed‐forward compensation (FFC) to prevent the stator flux oscillation from affecting the rotor current control. The dual‐sequence FFC is proposed for the asymmetrical LVRT of the DFIG. To reduce the rotor voltage increase due to the FFC, the controllable resistive‐type fault current limiter (CRTFCL) is implemented at the stator side to improve damping to the stator flux oscillation. The resistance of the CRTFCL is controlled based on the ramp function to relieve oscillations resulted from the switch‐out of the CRTFCL. With the dual‐sequence FFC and CRTFCL applied to the asymmetrical LVRT, analytical expressions of the stator current, rotor current, and rotor voltage are derived. The accuracy of the analytical expressions and the improved LVRT performance with the dual‐sequence FFC and the CRTFCL are verified based on the time‐domain simulations. © 2020 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [ABSTRACT FROM AUTHOR]