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The packaging technology for the medium‐voltage silicon carbide (SiC)‐metal oxide semiconductor field‐effect transistor (MOSFETs) has come a long way since its inception. Now, it is feasible to design half‐bridge power modules based on 10‐kV SiC‐MOSFETs for higher current applications. This paves the way for many application areas for these devices, particularly for medium‐voltage and high‐power applications. This paper presents a design of a modular medium‐voltage, high‐power isolated DC–DC converter enabled by these 10‐kV SiC‐MOSFETs‐based power modules. The design objectives are targeted at increasing the efficiency, power density, and interoperability. The proposed DC–DC converter is aimed for applications like DC distribution for the data centers, subsea power transmission, offshore wind farms, and photovoltaic energy transmission–distribution–coordination; electric ship DC power transmission; solid‐state distribution transformer, etc. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Theoretically, normally‐off silicon carbide (SiC) junction field‐effect transistors (JFETs) do not require a negative gate voltage supply because they are in an off‐state when the gate–source voltage is 0 V. However, most gate drivers for normally‐off SiC JFETs require not only a positive power supply for turning on the JFET but also a negative power supply for turning it off and maintaining a negative gate–source voltage to suppress a false turn‐on power loss caused by crosstalk during fast switching. Therefore, modifications of gate drivers increase complications and costs. In this study, a normally‐off SiC JFET gate driver, which can be realized using a simple circuit configuration with a single power supply, is proposed. To minimize undesirable crosstalk, the gate‐source voltage of the JFET is driven to a negative value and retained in the state for a long period of time. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Transistor aging occurs in nanoscale LSIs and is a factor that degrades large scale integration (LSI) performance. Because aging decreases the switching speed of transistors, LSIs ultimately malfunction due to the increase in the propagation delay. This paper proposes a procedure starting from the estimation of the aging amount at the metal‐oxide‐semiconductor field‐effect transistor (MOS FET) level to that at the gate level. The aging effect at the MOS FET level is extracted from changes in the periods of two special ring oscillators. The aging amount at the MOS FET is estimated by using a calculation model based on an RC circuit. The estimated aging amount is used to estimate the increase in propagation delay due to aging at the gate level. Results of circuit simulations showed that the proposed procedure produced estimations with an error rate of less than 4.6% for the increase in switching delay, and less than 0.6% for the increase in threshold voltage. For estimation of path delay, the range of the error rate was from –22.7 to +11.4%. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

We describe a readout module for radiation-sensing field-effect transistors. Three of these modules are currently being used for measuring the total accumulated dose in the silicon vertex detector (SVD) of the Belie experiment at KEKB B-meson factory in the High energy accelerator research organization (KEK), Japan. These modules have been in operation since August 2005. [ABSTRACT FROM AUTHOR]

This paper reports on the reliability improvement of Al-gate power GaAs-MESFET (FET) formed by the photoresist liftoff process (PLP). Al electromigration (EM) tolerance improvement with a higher deposition rate and lower outgas photoresist, a gate breakdown voltage (BVgd) improvement with fine recess control for the channel layer, and the mean time to failure (MTTF) at the 1-dB gain compression point in high-temperature RF operating life tests (HTRF) are described. We observed the parameters of the median time to failure (MTF) with high-temperature forward-bias tests (HTFB), as well as BVgd, and the gate current. The contributions of these parameters to MTTF are estimated by using an RF gate current simulation. © 2000 Scripta Technica, Electron Comm Jpn Pt 2, 83(7): 22–30, 2000 [ABSTRACT FROM AUTHOR]

The source-drain penetration (ALPEN) effect, which is a new α-particle induced soft error mechanism, was found and investigated by using a 3-dimensional simulation. When an α-particle penetrates the source-drain region of a short channel MOSFET, the funneling field extends from both electrodes and the channel potential becomes distorted, thereby causing a funneling current. Since this current causes a charge leakage, it causes ‘0’ → ‘1’ reverse mode soft error in the DRAM in addition to the conventional α-particle soft error. This error mechanism was also confirmed experimentally. The influence of this effect on future devices is predicted, and it has been shown that a device with a channel length shorter than 0.5 μm is influenced strongly by this effect. Therefore, it was concluded that this effect is an important factor in the scaling limit of a device. [ABSTRACT FROM AUTHOR]