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This article presents a reconfigurable integrated level shifted carrier‐based pulse width modulation (ILSC‐PWM) method for modular multilevel converters (MMCs). The principles of basic level shifted carrier‐based PWM (LSC‐PWM) methods such as phase disposition PWM (PD‐PWM), phase opposition disposition PWM (POD‐PWM) and alternate phase opposition disposition PWM (APOD‐PWM) methods are combined to develop the concept of reconfigurable ILSC‐PWM method. The main objectives of the proposed reconfigurable ILSC‐PWM method is to develop the pulse width modulated output voltage with both half‐wave and quarter‐wave symmetries and to reduce the total harmonic distortion (THD). A simplified mathematical approach is developed to formulate reconfigurable single ILSC wave for MMC with N number of submodules (SMs) per arm. The functionality and performance of the reconfigurable ILSC‐PWM method are carried out on three‐phase five‐level MMC in MATLAB/Simulink. A hardware prototype of single‐phase five‐level MMC is designed for experimental validation. The proposed ILSC‐PWM method is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field programmable gate array (FPGA). Computer Simulations and laboratory experimental results are presented. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Japan Proton Accelerator Research Complex aims at a megawatts-class proton accelerator facility. One of the promising solutions for increasing the beam power of the main ring is the converters of the main magnets with new ones for this upgrade. We have a plan to replace and develop the power converters of main magnets for this upgrade. According to develop the new power converter. We have developed a new control system for the new power converters. This control system consists of four parts: the current measuring device, the feedback control system, the gate pulse generator, and the slow control system. Considering a reproducibility in the mass production and the facilitation of the control algorithm, the digital control system is adopted. We will report the design of this control system and some test result with a new power converter for small quadrupole magnets. [ABSTRACT FROM AUTHOR]

The betatron tune, which is defined as the number of transverse oscillations in one turn of a ring accelerator, is one of the most important parameters. An undesired betatron tune increases the amplitude of the transverse oscillation so that many particles are lost from the ring sooner than designed. Since a betatron tune is controlled by the magnetic fields in the ring, the ripple of the magnet current directly displaces the betatron tune from its designated value. We have developed a system that corrects the betatron tune displacement using the measured magnet current at the Japan Proton Accelerator Research Complex main ring. We adopted field programmable gate arrays to convert from the measured magnet current to the betatron tune in real time. Using the system, we have decreased the fluctuation of the betatron tune $\sigma _{\nu }$ from $5.2\times 10^{-4}$ to $3.3\times 10^{-4}$ at the frequencies less than 250 Hz. [ABSTRACT FROM AUTHOR]

This paper describes the teaching and research of signal processing and communications systems that took place during the development of a real-time transceiver and radio channel testbed at Hokkaido University, Japan. Digital signal processing (DSP) concepts were taught and learnt during both the testbed system development and also the results gathering and analysis stages. The performance of a modern multiple antenna communications system is dependent on a number of key parameters, and the student interaction with such a real-time system can assist in the understanding of key but often abstract theoretical concepts. The communications algorithm and architecture overview on a signal processing board containing a Xilinx field programmable gate array (FPGA) and Analog Devices TigerSharc DSP is detailed. The lessons learned and potential uses of the testbed in both teaching and research are also described. [ABSTRACT FROM AUTHOR]

Abstract: A major upgrade of the KEKB factory (Tsukuba, Japan) is foreseen until 2013, aiming at a luminosity of up to , which is about 40 times the present value. Accordingly, a similar increase is expected for trigger rate and occupancy of the Silicon Vertex Detector (SVD). The current readout system has a shaping time of 800ns, no multi-event memory and thus requires a trigger within this period. As it already operates at its limit, it obviously has to be replaced for the upgrade. We developed a readout system using the APV25 chip with a shaping time of 50ns and an integrated analog pipeline. By taking six consecutive samples of the shaper output and processing these data with FPGAs on a VME module we can determine timing information of the hits with a precision of about 3ns RMS, which enables occupancy reduction and thus eases subsequent track finding. Thanks to reading several samples the system can tolerate a trigger jitter of up to clocks. A dedicated pipelined data processor is implemented for each input, which encodes position, pulse height and time information of a hit in a single 32 bit word. The acceptable trigger rate is limited by the time needed to read out six samples from the APV25. [Copyright &y& Elsevier]