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International audience; Synthetic biology is an emerging scientific field that promotes the standardized manufacturing of biological components without natural equivalents. Its goal is to create artificial living systems that can meet various needs in health care, nanotechnology and energy. Most works are currently focused on the individual bacterium as a chemical reactor. Our project, SynBioTIC, addresses a novel and more complex challenge: shape engineering, i.e. the redesign of natural morphogenesis toward a new kind of " developmental 3D printing ". Potential applications include organ growth, natural computing in biocircuits, or future vegetal houses. Using realistic agent-based simulations of bacterial mats, we experiment with mechanisms allowing cell assemblies to collectively self-repair and develop complex structures. To create multicellular organisms that exhibit specific shapes (a completely original task) we construe their development iteratively by combining basic processes such as homeostasis, segmentation, and controlled proliferation in silico. We use the E. coli simulator Gro 1 , a physico-chemical computation platform offering reaction-diffusion and collision dynamics solvers. The synthetic " bioware " of our model executes a set of rules, or " genome " , in each cell. Cells can differentiate into several predefined types associated with specific actions (divide, tumble, emit signal, die, etc.). Transitions between types are triggered by conditions involving internal and external sensors that detect various protein levels inside and around the cell. There is no direct molecular signaling between two neighboring bacteria, only indirect communication via morphogen diffusion and the mechanical constraints of 2D packing. In any case, the overall architecture emerges in a purely endogenous fashion. For now, cell behaviors are set by rules hand-coded in the Gro script language. Starting from a single bacterium, our artificial creatures execute a series of developmental stages. First, isotropic proliferation produces a roughly circular population characterized by homeostatic activity (black and white cores in Fig. 1a,b). This is based on leader cells emitting a morphogen, while other cells continually divide and die at the periphery where the morphogen concentra-1 Jang, Oishi, Egbert & Klavins (2012) ACS Syn Biol, 1:365–74. (a) (b) (c) Figure 1: Example of simulated organisms. (a,b) T and L shapes. Each limb of the organism stems from differentiated precursor cells. Starting from a four-pointed star, this makes it possible to introduce a " divergence of homology " through different parameter values in each limb, whether unequal lengths or complete silencing. (c) Three-pointed star shape. Here, limb growth is undifferentiated and the organism exhibits radial symmetry. tion drops. Then, the central region of the disc differentiates from the crown. Each cell also contains an oscillatory mechanism acting like a internal clock. In the crown, these oscillators are synchronized, i.e. characterized by a uniform phase. At this stage, a new wave of morphogen is triggered by a randomly activated cell on the crown, and rapidly propagates (suppressing any competitor wave). The encounter between the wave front and the current state of the oscillator determines whether each cell differentiates, and into what type. The period of oscillations controls the number of segments that can appear. Finally, precursor cells emerge at the periphery of these segments and stimulate new local proliferation , which eventually triggers limb growth in a way similar to the apical meristem of plant shoots (Fig. 1c). Applying this mechanism to two segments and two precursors , North and South, then on the equator that they form (areas of equal morphogen concentration), the system gives rise to a second pair, East and West, i.e. four differentiated seeds in total. This makes it possible to control the growth and features of single appendages. The L and T shapes of Fig. 1 exemplify this " divergence of homology " : some precursors are inhibited while others create limbs of varying size. Such morphogenetic phenotypes allow us to envision more complex shapes made of an array of cores and limbs, by iterating the above processes. Most importantly, they open the door to an evolutionary (" evo-devo ") exploration.

Complex systems often show forms of organisation where a clear-cut hierarchy of levels with a well-defined direction of information flow cannot be found. In this paper we propose an information-theoretic method aimed at identifying the dynamically relevant parts of a system along with their relationships, interpreting in such a way the system’s dynamical organisation. The analysis is quite general and can be applied to many dynamical systems. We show here its application to two relevant biological examples, the case of mammalian cell cycle network and of Mitogen Activated Protein Kinase (MAPK) cascade. The result of our analysis shows that the elements of the mammalian cell cycle network act as a single compact group, whereas the MAPK system can be decomposed into two dynamically distinct parts, with asymmetric information flows.

This paper discusses the notion of “core bio-inspired services” - low-level services providing basic bio-inspired mechanisms, such as evaporation, aggregation or spreading - shared by higher-level services or applications. Design patterns descriptions of self-organising mechanisms, such as gossip, morphogenesis, or foraging, show that these higher-level mechanisms are composed of basic bio-inspired mechanisms (e.g. digital pheromone is composed of spreading, aggregation and evaporation). In order to ease design and implementation of self-organising applications (or high-level services), by supporting reuse of code and algorithms, this paper proposes BIO-CORE, an execution model that provides these low-level services at the heart of any middleware or infrastructure supporting such applications, and provides them as “core” built-in services around which all other services are built.

International audience; For a long time, the code generation from domain-specific and/or model-based languages to implementation ones remained manual and error-prone. The use of modeling was required in the early stages of development to ease the design and communicate intents, but because of the manual implementation, there were no traceability and no formal link with the final code. Model-Driven Development (MDD) was unable to win its audience. Today, models constructed with UML have an equivalent representation in XML. And thanks to XML technologies, manipulating models for data mining, transformation or code generation becomes possible. MDD is now commonly used within the software community. Next, for the hardware community, this work will empower the use of MDD in hardware design and simulation. It offers a completely operational framework based on OMG standards: UML and MARTE.

International audience; We present a model for the travelling salesman problem (TSP) solved using the ant colony optimisation (ACO), a bio-inspired mechanism that helps speed up the search for a solution and that can be applied to many other problems. The natural complexity of the TSP combined with the self-organisation and emergent behaviours that result from the application of the ACO make model-checking this system a hard task. We discuss our approach for modelling the ACO in a well-known probabilistic model checker and describe results of verifications carried out using our model and a couple of probabilistic temporal properties. These results demonstrate not only the effectiveness of the ACO applied to the TSP, but also that our modelling approach for the ACO produces the expected behaviour. It also indicates that the same modelling could be used in other scenarios.

International audience; The ongoing OMG standard on the "Semantics of a Foundational Subset for Executable UML Models" identifies a subset of UML (called fUML, for Foundational UML), for which it defines a general-purpose execution model. This execution model therefore captures an executable semantics for fUML, providing an unambiguous basis for various kinds of model-based exploitations (model transformation, code generation, analysis, simulation, debugging etc.). This kind of facility is of great interest for the domain of real time systems, where analysis of system behavior is very sensible. One may therefore wonder if the general-purpose execution model of fUML can be used to reflect execution semantics concerns of real-time systems (e.g., concurrency, synchronization, and scheduling.). It would practically mean that it is possible to leverage on this precise semantic foundation (and all the work that its definition implied) to capture the precise execution semantics of real-time systems. In this paper, we show that this approach is not directly feasible, because of the way concurrency and asynchronous communications are actually handled in the fUML execution model. However, we show that introducing support for these aspects is technically feasible and reasonable in terms of effort and we propose lightweight modifications of the Execution model to illustrate our purpose.

International audience; Embedded systems' complexity and amount of distinct functionalities have increased over the last years. To cope with such issues, the projects' abstraction level is being continuously raised, and, in addition, new design techniques have also been used to shorten design time. In this context, Model-Driven Engineering approaches that use UML models are interesting options to design embedded systems, aiming at code generation of software and hardware components. Source code generation from UML is already supported by several commercial tools for software. However, there are only few tools addressing generation code using hardware description languages, such as VHDL. This work proposes an approach to generate automatically VHDL source code from UML specifications. This approach is supported by the GenERTiCA tool, which has been extended to support VHDL code generation. To validate this work, a use case focused in maintenance systems attended by embedded systems is presented.

IFIP Working Group 10.2 was pleased to sponsor DIPES 2010, the IFIP Conference on Distributed and Parallel Embedded Systems. The conference was held in Brisbane, Australia during September 20-22, 2010 as part of the IFIP World Computer Conference.

International audience; Concurrent software is difficult to verify. Because the thread schedule is not controlled by the application, testing may miss defects that occur under specific thread schedules. This problem gave rise to software model checking, where the outcome of all possible thread schedules is analyzed. Among existing software model checkers for multi-threaded programs, Java PathFinder for Java bytecode is probably the most flexible one. We argue that compared to C programs, the virtual machine architecture of Java, combined with the absence of direct low-level memory access, lends itself to software model checking using a virtual machine approach. C model checkers, on the other hand, often use a stateless approach, where it is harder to avoid redundancy in the analysis. Because of this, we found it beneficial to prototype a concurrent algorithm in Java, and use the richer feature set of a Java model checker, before moving our implementation to C. As the thread models are nearly identical, such a transition does not incur high development cost. Our case studies confirm the potential of our approach.

International audience; In this paper we present a novel two-stage method to realize a lightweight but very capable hardware implementation of a Learning Classifier System for on-chip learning. Learning Classifier Systems (LCS) allow taking good run-time decisions, but current hardware implementations are either large or have limited learning capabilities. In this work, we combine the capabilities of a software-based LCS, the XCS, with a lightweight hardware implementation, the LCT, retaining the benefits of both. We compare our method with other LCS implementations using the multiplexer problem and evaluate it with two chip-related problems, run-time task allocation and SoC component parameterization. In all three problem sets, we find that the learning and self-adaptation capabilities are comparable to a full-fledged system, but with the added benefits of a lightweight hardware implementation, namely small area size and quick response time. Given our work, autonomous chips based on Learning Classifier Systems become feasible.

Look deep into nature and you will understand everything better,” advised Albert Einstein. In recent years, the research communities in computer science, engineering, and other disciplines have taken this message to heart, and a relatively new field of “biologically inspired computing” has been born. Inspiration is being drawn from nature, from the behaviors of colonies of ants, of swarms of bees, and even the human body. This new paradigm in computing takes many simple autonomous objects or agents and lets them jointly perform a complex task, without having the need for centralized control. In this paradigm, these simple objects interact locally with their environment using simple rules. Applications include optimization algorithms, communications networks, scheduling and decision making, supply-chain management, and robotics, to name just a few. There are many disciplines involved in making such systems work: from artificial intelligence to energy-aware systems. Often these disciplines have their own field of focus, have their own conferences, or only deal with specialized sub-problems (e.g., swarm intelligence, biologically inspired computation, sensor networks). The Third IFIP Conference on Biologically Inspired Collaborative Computing aimed to bridge this separation of the scientific community and bring together researchers in the fields of organic computing, autonomic computing, self-organizing systems, pervasive computing, and related areas.

International audience; Embedded systems have developed from single microcontrollers to networked sys-tems and are moving further on to large open systems. As an example, automotive electronics started as a single microcontroller for engine control to develop into a local network of 50 and more electronic control units connected via several network standards and gateways which are found in current cars. These networks will be ex-tended by open wireless car-to-car or car-to-infrastructure communication enabling completely new functionality, such as advanced driver assistance systems that report approaching cars that could cause an accident. Other examples are found in health-care, where patients are monitored at home connected to a hospital data base and monitoring system rather than staying in the hospital for that purpose, or in smart buildings where different control functions are integrated to minimize energy con-sumption and adapt consumption to the available energy, or in energy supply net-works that are optimized to include renewable energy production. In all these cases we observe a transition from local closed networks with a single systems integrator controlling all design aspects (such as an automotive manufacturer) to larger open networks with many independent functions and different integrators following differ-ent design objectives. The Internet plays an important role supporting that trend. Unlike closed networks with a defined topology, such systems change over the life-time of a system.

International audience; Increasingly, embedded systems designers tend to use Application Specific Instruction Set Processors (ASIPs) during the design of application specific systems. However, one of the design metrics of embedded systems is the time to market of a product, which includes the design time of an embedded processor, is an important consideration in the deployment of ASIPs. While the design time of an ASIP is very short compared to an ASIC it is longer than when using a general purpose processor. There exist a number of tools which expedite this design process, and they could be divided into two: first, tools that automatically generate HDL descriptions of the processor for both simulation and synthesis; and second, tools that generate instruction set simulators for the simulation of the hardware models. While the first one is useful to measure the critical path of the design, die area, etc. they are extremely slow for simulating real world software applications. At the same time, the instruction set simulators are fast for simulating real world software applications, but they fail to provide information so readily available from the HDL models. The framework presented in this paper, RACE, addresses this issue by integrating an automatic HDL generator with a well-known instruction set simulator. Therefore, embedded systems designers who use our RACE framework will have the benefits of both a fast instruction set simulation and rapid hardware synthesis at the same time.