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This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-°oating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5V and consumes only 357nW of power. The proposed circuit was simulated in a 0.18-μm TSMC [ABSTRACT FROM AUTHOR]

A 12th-order low voltage tunable differential complex filter for bluetooth and Zigbee applications is proposed in this paper. The filter is based on improved controllable transconductors operating with the ultra-low supply voltage of 0.5 V. Simulation results using a triple-well 0.13 μm CMOS technology verify the filter operation fulfilling all the requirements for the complex filtering stage in bluetooth or Zigbee receivers. The in-band group delay variation is 0.79 μs for bluetooth and 0.46 μs for Zigbee. The image rejection ratio is greater than 71 dB and the achieved in-band spurious free dynamic range is 42 dB. [ABSTRACT FROM AUTHOR]

A generalized structure that is capable of implementing power-law filters derived from 1st and 2nd-order mother filter functions is presented in this work. This is achieved thanks to the employment of Operational Transconductance Amplifiers (OTAs) as active elements, because of the electronic tuning capability of their transconductance parameter. Appropriate design examples are provided and the performance of the introduced structure is evaluated through simulation results using the Cadence Integrated Circuits (IC) design suite and Metal Oxide Semiconductor (MOS) transistors models available from the Austria Mikro Systeme (AMS) 0.35 μ m Complementary Metal Oxide Semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

Configurations of companding filters with large time-constants are presented in this paper. For this purpose, novel Log-Domain and Sinh-Domain integrators are introduced, where the realization of time-constants is achieved through a capacitor multiplication. The same concept has been followed in the case of realization of the Log-Domain and Sinh-Domain equivalents of passive elements. The performance of the derived filters has been evaluated through simulation and comparison results using the Analog Design Environment of the Cadence software and MOS transistors parameters provided by the TSMC 180 nm CMOS process. As a design example, a fourth-order bandpass filter has been realized for extracting the alpha, beta, gamma, and theta waves of an electroencephalogram. [ABSTRACT FROM AUTHOR]

Nowadays the necessity of having low-voltage operation and low-power consumption is essential for electronic devices, particularly for portable electronics. Therefore, this paper presents a new ultra-low-voltage CMOS topology for a differential difference current conveyor (DDCC) based on the bulk-driven (BD) principle. Due to the use of the BD technique, the proposed circuit is capable of working with a low supply voltage of ±0.3 V and consumes about 18.6 μW with a wide input common-mode range. The proposed BD-DDCC is suitable for ultra-low-voltage low-power applications. As application examples, a voltage-mode multifunction biquadratic filter based on two BD-DDCCs and four grounded passive elements, and a fourth-order band-pass filter are presented. All passive elements of both applications are grounded, which is advantageous for monolithic integration. Also, the input voltage signals are applied directly to the high input impedance terminals, which is a desirable feature for voltage-mode operation. The simulations were performed with PSPICE using the TSMC 0.18 μm n-well CMOS technology to prove the functionality and attractive results of the proposed circuit. [ABSTRACT FROM AUTHOR]

A novel low-voltage n-th order Follow the Leader Feedback (FLF) multifunction filter topology, realized by employing the concept of Sinh-Domain filtering, is introduced in this manuscript. The realization of the Sinh-Domain filter topology is achieved by utilizing the corresponding FLF conventional topology and performing a transposition into Sinh-Domain, through an appropriate set of complementary operators. The design offers the benefit of absence of any restriction concerning the order of the Sinh-Domain multifunction filter. As an example, a 5th-order Sinh-Domain multifunction filter is designed for EEG signal recognition. Simulation results for the filter have shown a dynamic range (DR) of 68.82 dB and power consumption 25.2 nW. [ABSTRACT FROM AUTHOR]

Square-root-domain (SRD) CMOS analog realization of a single cell architecture of the complex Temporal Derivative Cellular Neural Networks (TDCNNs) is introduced in this paper. TDCNN initiates time derivative 'diffusion' between CNN cells for non-separable spatiotemporal filtering applications, where the input to the CNN is an image that changes over time. The evaluation of the performance of the complex SRD TDCNN cell has been done using the Cadence Orcad software with TSMC 0.18-μm CMOS process model parameters. The provided simulated results confirm the validity of the theory. [ABSTRACT FROM AUTHOR]

This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5 V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter's cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13µm CMOS process and is operated under a 0.5 V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software. [ABSTRACT FROM AUTHOR]

SUMMARY A new systematic method for designing Sinh-Domain filters is introduced in this paper. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh-Domain. The proposed method offers the benefits of facilitating the design procedure of high-order Sinh-Domain filters and of the absence of any restriction concerning the type and/or the order of the realized filter function. As an example, a third-order Sinh-Domain leapfrog filter is designed by employing the proposed set of operators. Two possible realizations are given and their performance has been evaluated and compared through simulation results. Copyright © 2011 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A structure suitable for implementing power-law low-pass and high-pass filter transfer functions is presented in this work. Through the utilization of a field-programmable analog array device, full programmability of the characteristics of the intermediate stages, as is required for realizing the rational integer-order transfer function that approximates the corresponding power-law function, was achieved, making the structure versatile. In addition, a comparison between power-law and fractional-order filters regarding the effect of the non-integer order was performed. The presented design examples are fully supported by experimental results. [ABSTRACT FROM AUTHOR]

A simple and direct procedure for implementing fractional-order filters with transfer functions that contain Laplace operators of different fractional orders is presented in this work. Based on a general fractional-order transfer function that describes fractional-order low-pass, high-pass, band-pass, band-stop and all-pass filters, the introduced concept deals with the consideration of this function as a whole, with its approximation being performed using a curve-fitting-based technique. Compared to the conventional procedure, where each fractional-order Laplace operator of the transfer function is individually approximated, the main offered benefit is the significant reduction in the order of the resulting rational function. Experimental results, obtained using a field-programmable analog array device, verify the validity of this concept. [ABSTRACT FROM AUTHOR]

The gain and phase responses of the delay element e-τs\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$e^{-\sqrt{\tau s}}$$\end{document} are related through a non-linear relation, unlike the conventional e-τs\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$e^{-{\tau s}}$$\end{document} delay element where the gain is constant over the entire frequency range. This makes this fractional-order element attractive for describing the dynamics of systems with dead-time zone. In this work, the transfer function of this element is approximated through a rational integer-order function resulting from a curve-fitting based method. The performed comparison with the literature shows that the curve-fitting based approximation method achieves errors in gain and phase less than 0.3dB and 2o, respectively, while the available method in the literature achieves 3.7dB and 8o, respectively. The behavior of some filters involving this delay element is evaluated and it is demonstrated that the implementation of these filters can be performed by the same circuit core, simply by adjusting the coefficients of the approximation transfer function. The findings of this work are supported by MATLAB simulation results and, also, by experimental results obtained through the utilization of a Field Programmable Analog Array device. [ABSTRACT FROM AUTHOR]

A novel procedure for the circuit implementation of the driving-point impedance of frequency-domain material models, constructed from fractional-order elements of arbitrary type and order, is introduced in this work. Following this newly introduced concept, instead of emulating separately each fractional-order element in the model under consideration, the direct emulation of the complete model can be achieved through the approximation of the total impedance function. The magnitude and phase frequency responses of the impedance function are first extracted and approximated through curve-fitting-based techniques. A rational integer-order driving-point impedance function is then obtained and realized using appropriately configured passive and/or active topologies. Comparison between the conventional method and the proposed method reveals that the achieved benefit is the significant reduction of the passive and/or active components count. Verification of the introduced concept is performed through circuit simulation results using OrCAD PSpice in the case of a root/stem/electrode interface model, as well as through experimental results where the driving-point input impedance of the human respiratory system under different health conditions is synthesized on a Field-Programmable Analog Array device. [ABSTRACT FROM AUTHOR]

In the current state of the art, WiFi-alike standards require achieving a high Image Rejection Ratio (IRR) while having low power consumption. Thus, quadrature structures based on passive ring mixers offer an attractive and widely used solution, as they can achieve a high IRR while being a passive block. However, it is not easy for the designer to know when a simple quadrature scheme is enough and when they should aim for a double quadrature structure approach, as the latter can improve the performance at the cost of requiring more area and complexity. This study focuses on the IRR, which crucially depends on the symmetry between the I and Q branches. Non-idealities (component mismatches, parasitics, etc.) will degrade the ideal balance by affecting the mixer and/or following/previous stages. This paper analyses the effect of imbalances, providing the constraints for obtaining a 40 dB IRR in the case of a conversion from a one-hundred-megahertz signal to the five-gigahertz range (upconversion) and vice versa (downconversion) for simple and double quadrature schemes. All simulations were carried out with complete device models from 65 nm standard CMOS technology and also a post-layout Monte Carlo analysis was included for mismatch analysis. The final section includes guidelines to help designers choose the most adequate scheme for each case. [ABSTRACT FROM AUTHOR]

A new category of fractional-order filters, realized without employing a fractional-order Laplacian operator is introduced in this work. This can be achieved through the utilization of an efficient curve fitting method which approximates the frequency-domain behavior of the filter and transposes the fractional-order transfer function into the integer-order domain. Thus, the procedure results in a rational integer-order transfer function and its implementation is possible using conventional integer-order realization techniques. Therefore, there is no need for fractional-order elements to realize this class of filters. Design examples of this new kind of filters are presented with the derived simulation and experimental results confirming their correct performance. [ABSTRACT FROM AUTHOR]

In this paper, a new current-mode instrumentation amplifier with electronic tuning and low-voltage operation capabilities is presented. Simplicity is other important feature so that the whole circuit is composed of only 20 transistors. All the above have been achieved using MOS transistors biased in the sub-threshold region. The required current-controlled gain stage has been implemented using an appropriate translinear loop which is fed by the output of a current subtraction stage, realized through the employment of flipped voltage follower based current-mirrors. The performance of the presented amplifier is evaluated through simulation results, using the Cadence suite and MOS transistors models provided by the Austria Mikro Systeme 0.35 μ m CMOS process. The differential gain was 20 – 40 dB , the Common-Mode Rejection Ratio (CMRR) was 44.4 – 48.9 dB , achieved at power dissipation 72.75 – 386.1 nW. The bandwidth was 7 kHz and the Total Harmonic Distortion (THD) was 2 % for an input signal with amplitude equal to 550 pA. As an application example, the proposed current-mode instrumentation amplifier has been employed for removing the noise component in electrocardiogram signals. [ABSTRACT FROM AUTHOR]

A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. [ABSTRACT FROM AUTHOR]

Novel double-dispersion models based on power-law filters are introduced in this work. These models are based on standard first-order and/or second-order low-pass filter transfer functions (denoted as mother functions) and do not require the employment of the fractional-order Laplacian operator. An attractive benefit, from the flexibility point of view, is that the number of parameters, which must be determined via optimization routines, depends on the selected combinations of mother filters. The validity of the proposed models is verified through fitting experimental bio-impedance data of fruit samples measured within a two-day period of time. The accuracy of the proposed models is compared with the classical double-dispersion Cole–Cole model for the same data. [ABSTRACT FROM AUTHOR]

Novel structures with adjustable characteristics, capable of performing the process where the vowel waveform is derived from a pulse train produced by the vibrating vocal folds and vice versa, are introduced in this work. Various design techniques are exploited to implement the required resonator and anti-resonator stages. The offered design flexibility and versatility are achieved through the employment of suitable active elements which offer electronically controlled characteristics in the resonator and anti-resonator stages, such as the Operational Transconductance Amplifiers, or through the employment of stages where their frequency behavior is digitally programmed, such as the Configurable Analog Modules included in a Field Programmable Analog Array device. The provided post-layout simulation and experimental results confirm the correct operation of the introduced structures in both the frequency and time domains. [ABSTRACT FROM AUTHOR]

ABSTRACT Two new full‐wave rectifiers (FWRs) based on two plus‐type second‐generation current conveyors are proposed in this paper. Also, the proposed FWR structures comprise two diodes and two grounded resistors without matching conditions. They are not affected from any bias voltage(s) and/or current(s); thus, they eliminate the need for extra circuitry. One of the proposed FWRs provides positive rectification, while the other offers negative rectification. Both proposed FWRs have high input impedance and gain. Simulation results are obtained through the SPICE program, and experimental results are provided. [ABSTRACT FROM AUTHOR]

A novel scheme suitable for the emulation of fractional-order capacitors and inductors of any order less than 2 is presented in this work. Classically, fractional-order impedances are characterized in the frequency domain by a fractional-order Laplacian of the form s ± α with an order 0 < α < 1 . The ideal inductor and capacitor correspond, respectively, to setting α = ± 1 . In the range 1 < α < 2 , fractional-order impedances can still be obtained before turning into a Frequency- Dependent Negative Resistor (FDNR) at α = ± 2 . Here, we propose an electronically tunable fractional-order impedance emulator with adjustable order in the full range 0 < α < 2 . The values of the emulated capacitance/inductance, as well as the bandwidth of operation, are also electronically adjustable. The post- layout simulation results confirm the correct operation of the proposed circuits. [ABSTRACT FROM AUTHOR]

A novel structure of multi-phase sinusoidal oscillator is introduced in this work. Its realization is based on the employment of the shadow filtering technique, which offers the benefit of the independent tuning of the oscillation frequency as well as of the condition of oscillation through external amplifiers. The core of the oscillator remains unchanged during the tuning process and, therefore, the introduced concept achieves design flexibility and modularity. A design example is provided, where the implementation of the oscillator is performed through the utilization of Current Feedback Operational Amplifiers as active elements, and the behavior of the oscillator is evaluated through simulation results obtained using the OrCAD PSpice suite. In addition, the provided experimental results support the findings of this work. [ABSTRACT FROM AUTHOR]

Presents a correction to the article 'On the exact realization of LOG-domain elliptic filters using the signal flow graph approach' on page 770-774 of volume 49, number 12, December 2002 issue of 'IEEE Transactions on Circuits and Systems II.' Error on reference 4.

Provides a corrected reprint to the article entitled 'A Systematic Design Procedure for Square-Root-Domain Circuits Based on Signal Flow Graph Approach,' published in the May 2003 issue of the 'IEEE Transactions on Circuits and Systems' journal.

This paper reviews amplifier-based oscillator topologies and introduces new ones while reporting all possible circuits that can be obtained from some of them using exhaustive searching. Second-order as well as third-order RC and RLC oscillators are reported and selected circuits are designed and experimentally verified. Incorporating non-ideal and nonlinear effects into the modeling of these amplifier-based oscillators are demonstrated. [ABSTRACT FROM AUTHOR]

In this Letter we highlight some fundamental errors in the paper "Origin of the Curie–von Schweidler law and the fractional capacitor from time-varying capacitance" [J. Pow. Sources 532 (2022) 231309] by V. Pandey. In particular, with the use of the convolution integral of linear time-varying capacitance with the time-derivative of voltage (i.e. Eq (9) as suggested by the author), one ends up with step voltage function generating a constant current on a capacitive device, which is not true. We also question that a step voltage results in zero charge according to the r.h.s. of Eq. (9), but in reality it is well known that there is a charge build up in response to such an excitation applied on capacitive devices. This renders the rest of the manuscript questionable. Other inconsistencies are also presented and discussed. • Inconsistencies in Q (t) = C (t) ∗ V ̇ (t) of [J. Pow. Sources 532 (2022) 231309]. • Capacitances add up in parallel in the frequency domain, not in the time domain. • No dimensional inconsistency arises when applying the convolution theorem. [ABSTRACT FROM AUTHOR]

Non-integer power-law all-pass transfer functions, are approximated by suitable integer-order transfer functions in this work. The derivation of the integer-order transfer functions is based on the analytic expansion of the (non-integer) power-law transfer functions through the utilization of the binomial theorem. The offered benefit is the derivation of stable integer-order transfer functions. This study is supported by experimental results, obtained using a Field Programmable Analog Array device, after the employment of curve fitting based approximation techniques. [ABSTRACT FROM AUTHOR]

We seek to generalize and study the well-known Warburg impedance element, which has an impedance proportional to 1 / s (s = j ω is the complex frequency), to a two-port impedance network. For this purpose, we consider an infinite binary tree structure inside which each impedance is treated as a two-port network. We obtain a Warburg impedance matrix, which is both symmetrical and reciprocal, and study its equivalent circuit behavior. Interestingly, the equivalent circuit contains two resistors and a Cole–Davidson type impedance proportional to 1 + 2 / (τ s) , where τ is a time constant. Simulation results of the Warburg impedance matrix and its implementation in a resonance circuit are provided and discussed. [ABSTRACT FROM AUTHOR]

• Modified CPE impedance using the complex function s α , β = j β ω α instead of s α = (j ω) α . • Phase and magnitude are decoupled from each other in modified CPE. • Modified CPE is suitable for fitting non-KK compliant spectral data. The success of fractional-order fractance (FOF) as a modeling tool in (photo)bio(electro)chemical systems can be readily gauged by the large body of research work that has been conducted over the past few years in terms of materials fabrication, building integer-order emulators of their behavior, as well as applications in filter design, controller design, modeling of energy storage devices and biomaterials. The impedance of FOF has the general form Z α (s) = k α s α where k α and α are real constant and s = j ω is the complex Laplace number. In this work, we investigate the possibility of decoupling the magnitude and phase properties of a FOF, and the application of this modified circuit element in the modeling of spectral electrochemical data. The proposed modification relies on the complex parametric function j β ω α = j β - α s α which can been viewed as a phase-shifted version of s α = (j ω) α by a β -dependent constant angle. This extra degree of freedom is expected to be useful in facilitating the modeling of more complex systems in which the classical FOF fails, and is here verified on the low-frequency response of a lithium-ion battery showing unstationary and/or nonlinear behavior. [ABSTRACT FROM AUTHOR]

Fractional-order lead/lag compensator realizations, using Operational Transconductance Amplifiers as active blocks, are presented in this paper. Two different types of fractional-order transfer functions, derived from the integer-order lead/lag compensator transfer function, are used to describe the behavior of the fractional-order compensator. Both types are approximated using the Padé approximation tool, and are expressed by the same form of rational integer-order transfer function. This means that both types can be implemented using the same active core, which is an important advantage from the design versatility point of view. From the design flexibility point of view, the attractive feature is that both types offer electronic adjustment of their characteristics through the appropriate tuning of the DC bias currents. Simulation results, derived using the Cadence IC design suite and the design kit of the Austria Mikro Systeme 0.35 μ m CMOS process, are used for evaluating the performance of the presented designs. [ABSTRACT FROM AUTHOR]

Ultra-low-voltage sinh-domain implementation of delayed inertial neuron is introduced in this paper. The complex dynamical behavior of the neuron has been verified using three different activation functions, namely tanh, unipolar sigmoidal and bipolar sigmoidal. The networks containing two and four neurons have been designed, and their complex dynamical behavior has also been verified. The proposed implementation vis-à-vis the already reported designs offers the benefits of: (1) low-voltage operation, (2) integrability, due to resistor-less design and the employment of only grounded components, (3) electronic tunability of performance parameters by external currents, which adds flexibility to the proposed designs even after their final fabrication, (4) absence of inductors as, in contrast to reported designs, the delay has been implemented using component substitution method where inductors have been replaced by emulated inductors and (5) low-power implementation due to the inherent class AB nature of sinh-domain technique. Besides, for the first time, the complex dynamical behavior of four-neuron delayed inertial network has been implemented and its functioning for different activations functions has been considered and verified. HSPICE simulator tool and TSMC 130 nm CMOS process were used to evaluate and verify the correct functioning of the model. [ABSTRACT FROM AUTHOR]

This paper introduces a fractional-order eardrum Type-II model, which is derived using fractional calculus to reduce the number of elements compared to its integer-order counterpart. The proposed fractional-order model parameters are extracted and compared using five meta-heuristic optimization techniques. The CMOS implementation of the model is performed using the Design Kit of the Austria Mikro Systeme (AMS) 0.35 μ m CMOS process, while the simulations have been performed using the Cadence IC design suite. [ABSTRACT FROM AUTHOR]

The fractional-order model of a phantom electroencephalographic system, at various distances between electrodes, is realized using appropriate decomposition of the rational transfer functions which approximate the highpass filters that describe its dynamics. The main offered benefits, in comparison to the corresponding straightforward implementations of the rational transfer functions, are the capability of monolithic implementation due the minimization of the maximum value of the required capacitances and, also, the reduced power consumption. The performance of the presented filter topologies is evaluated, at post-layout level, using the Cadence design suite. [ABSTRACT FROM AUTHOR]

Abstract Fractional-Order circuits and networks being a widely researched field lags in its development due to the non-availability of its basic building block i.e. Fractional-Order Element (FOE). The FOE besides being compact and having wide frequency range should also be integrable with the Integrated Circuit (IC). In this paper, a detailed survey of single and multi-component FOE implementations has been carried out. The survey implies that a single component FOE is more suited for integration with the conventional circuitry but a market fit device is still a topic of research. Some future prospects and areas of research for the implementation of FOE have also been indicated in the paper. In addition, a survey of applications of single and multi-component FOE has also been included in the paper. [ABSTRACT FROM AUTHOR]

Supercapacitors are mostly recognized for their high power density capabilities and fast response time when compared to secondary batteries. However, computing their power in response to a given excitation using the standard formulæof capacitors is misleading and erroneous because supercapacitors are actually non-ideal capacitive devices that cannot be characterized with a single constant capacitance. In this study we show how to estimate accurately the time-domain power and energy of supercapacitors in response to any excitation signal represented in terms of its Fourier series coefficients with the sole knowledge of the frequency-domain impedance parameters of the device. The presented theory is first verified and validated with Spice simulations conducted on an RC network emulating the behavior of a circuit consisting of a resistance (R s) in series with a constant phase element (CPE) of fractional impedance Z CPE = 1 / (s C α). Then we do the same for a commercial supercapacitor modeled as an R s -CPE circuit, and subjected to both a periodic triangular voltage waveform and a random voltage excitation. The results are conclusive and very promising for adopting the proposed procedure to estimate the power and energy performance of supercapacitors in response to real-world charging and discharging signals. • Estimation of time-domain behavior of supercapacitors in response to any arbitrary excitation. • Verification of the procedure on an RC network emulating the behavior of a fractional-order circuit. • Verification of the procedure on a commercial supercapacitor. [ABSTRACT FROM AUTHOR]

This paper proposes a new design of a 2 α -order fractional-order band-pass filter with tunability feature. The proposed filter is approximated with the Continued Fraction Expansion and Matsuda second-order approximations. The realized filter transfer function is based on the Inverse Follow the Leader Feedback configuration, with Operational Transconductance Amplifiers as active elements. As a result, the order of the proposed filter can be adjusted by changing a single parameter, which is the bias current I bias . A comparison with the previous works is performed, showing the advantage of the electronic tuning feature using one bias current value in the proposed filter. Sensitivity analysis is conducted to investigate the effect of circuit parameters variation, such as capacitance and gain factors. Stability analysis is performed by studying the poles' location and movement versus the filter parameters. Besides, the effect of transistor mismatch is evaluated using Monte Carlo analysis. Matlab and Cadence software, with UMC technology of 0.13 μm CMOS, are used for verifying the proposed implementation. [ABSTRACT FROM AUTHOR]

The constant phase element (CPE) or fractional-order capacitor is an electrical device that has an impedance of the form Z (s) = 1 / C α s α , where C α is the CPE parameter and α is a fractional dispersion coefficient of values between 0 and 1. Here we show that in the time-domain the classical linear charge-voltage relationship of ideal capacitors, q = C · v , is not valid for CPEs. In fact the relationship is nonlinear and can be expressed as q = C (v ; C α , α) · v. We verify our findings using (i) circuit simulations of an integer-order emulator of a CPE, and (ii) experimental results from a commercial supercapacitor as well as an in-house fabricated device based on carbon film materials. [ABSTRACT FROM AUTHOR]